Patents by Inventor Prabhakaran Krishnamurthy

Prabhakaran Krishnamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7006962
    Abstract: A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic cones, and running respective instances of a delay prediction application on the logic cones on at least two computers in parallel.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: February 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: Saket Goyal, Santhanakrishnan Raman, Prabhakaran Krishnamurthy, Prasad Subbarao, Manjunatha Gowda
  • Patent number: 6880142
    Abstract: A method of calculating delay for a process variation includes finding a value for each of exactly two independent variables that results in a maximum or minimum variation of estimated cell delay plus net delay, calculating a variation of resistance from the value found for each of the exactly two independent variables, calculating a variation of capacitance from the value found for each of the exactly two independent variables, adding the calculated variation of resistance to a net resistance to generate a modified net resistance for a selected net, adding the calculated variation of capacitance to a net capacitance to generate a modified net capacitance for the selected net, and calculating the cell delay plus net delay from the modified net resistance and the modified net capacitance.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: April 12, 2005
    Assignee: LSI Logic Corporation
    Inventors: Qian Cui, Robert W. Davis, Sandeep Bhutani, Payman Zarkesh-Ha, John D. Corbeil, Jr., Prabhakaran Krishnamurthy
  • Patent number: 6845348
    Abstract: A method for modeling the output waveform of a cell driving a resistance-capacitance network includes multiple effective capacitances. A method of calculating Thevenin parameters includes the steps of (a) initializing estimates of effective capacitances Ceff1 and Ceff2, of a switching threshold delay t0, and of a slope delay deltat; (b) solving ramp response equations for t0 and deltat as a function of Ceff1 and Ceff2; (c) comparing the estimates of t0 and deltat with solutions for t0 and deltat found in step (b); and (d) replacing the estimates of t0 and deltat with the solutions for t0 and deltat if the solutions for t0 and deltat have not converged to the estimates of t0 and deltat.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: January 18, 2005
    Assignee: LSI Logic Corporation
    Inventors: Prasad Subbarao, Sandeep Bhutani, Charutosh Dixit, Prabhakaran Krishnamurthy
  • Publication number: 20040078765
    Abstract: A method of calculating delay for a process variation includes finding a value for each of exactly two independent variables that results in a maximum or minimum variation of estimated cell delay plus net delay, calculating a variation of resistance from the value found for each of the exactly two independent variables, calculating a variation of capacitance from the value found for each of the exactly two independent variables, adding the calculated variation of resistance to a net resistance to generate a modified net resistance for a selected net, adding the calculated variation of capacitance to a net capacitance to generate a modified net capacitance for the selected net, and calculating the cell delay plus net delay from the modified net resistance and the modified net capacitance.
    Type: Application
    Filed: October 16, 2002
    Publication date: April 22, 2004
    Inventors: Qian Cui, Robert W. Davis, Sandeep Bhutani, Payman Zarkesh-Ha, John D. Corbeil, Prabhakaran Krishnamurthy