Abstract: A fast buffer and switching regulator are combined in parallel in a master-slave loop topology to form a voltage regulator. The buffer circuit has a voltage sensing amplifier that senses the difference between the voltage at the output of the voltage regulator and a reference voltage. This voltage difference is amplified, and then input to a buffer that sources current to or sinks current from the output of the voltage regulator. The output of the buffer circuit is coupled to the switching converter which senses the changing buffer circuit output current. The switching converter changes its duty cycle to oppose the current from the buffer circuit. This is a master-slave loop topology wherein the buffer circuit is the master loop that quickly provides high levels of current to compensate for a voltage transient at the output of the voltage regulator, and the switching converter is the slave loop which eventually takes over from the master loop to meet the current output requirements of the voltage regulator.