Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

Abstract: Methods of forming memory structures are described. A metal film is deposited in the features of a structured substrate and volumetrically expanded to form pillars. A blanket film is deposited to a height less than the height of the pillars and the blanket film is removed from the top of the pillars. The height of the pillars is reduced so that the top of the pillars are below the surface of the blanket film and the process is optionally repeated to form a structure of predetermined height. The pillars can be removed from the features after formation of the predetermined height structure to form high aspect ratio features.

Abstract: Processing methods to form self-aligned high aspect ratio features are described. The methods comprise depositing a metal film on a structured substrate, volumetrically expanding the metal film, depositing a second film between the expanded pillars and optionally recessing the pillars and repeating the process to form the high aspect ratio features.

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

Abstract: A plasma reactor includes a processing chamber having a lower processing portion having an axis of symmetry and an array of cavities extending upwardly from the lower processing portion. A gas distributor couples plural gas sources to a plurality of gas inlets of the cavities, and the gas distributor includes a plurality of valves with each valve selectively connecting a respective gas inlet to one of the plural gas sources. Power is applied by an array of conductors that includes a respective conductor for each respective cavity with each conductor adjacent and surrounding a cavity. A power distributor couples a power source and the array of conductors, and the power distributor includes a plurality of switches with a switch for each respective conductor.

Abstract: Methods of forming memory structures are described. A metal film is deposited in the features of a structured substrate and volumetrically expanded to form pillars. A blanket film is deposited to a height less than the height of the pillars and the blanket film is removed from the top of the pillars. The height of the pillars is reduced so that the top of the pillars are below the surface of the blanket film and the process is optionally repeated to form a structure of predetermined height. The pillars can be removed from the features after formation of the predetermined height structure to form high aspect ratio features.

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

Abstract: A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.

Abstract: A plasma reactor includes a processing chamber having a lower processing portion having an axis of symmetry and an array of cavities extending upwardly from the lower processing portion. A gas distributor couples plural gas sources to a plurality of gas inlets of the cavities, and the gas distributor includes a plurality of valves with each valve selectively connecting a respective gas inlet to one of the plural gas sources. Power is applied by an array of conductors that includes a respective conductor for each respective cavity with each conductor adjacent and surrounding a cavity. A power distributor couples a power source and the array of conductors, and the power distributor includes a plurality of switches with a switch for each respective conductor.

Abstract: Processing methods to form self-aligned high aspect ratio features are described. The methods comprise depositing a metal film on a structured substrate, volumetrically expanding the metal film, depositing a second film between the expanded pillars and optionally recessing the pillars and repeating the process to form the high aspect ratio features.

Abstract: Implementations described herein generally relate to metal oxide deposition in a processing chamber. More specifically, implementations disclosed herein relate to a combined chemical vapor deposition and physical vapor deposition chamber. Utilizing a single oxide metal deposition chamber capable of performing both CVD and PVD advantageously reduces the cost of uniform semiconductor processing. Additionally, the single oxide metal deposition system reduces the time necessary to deposit semiconductor substrates and reduces the foot print required to process semiconductor substrates. In one implementation, the processing chamber includes a gas distribution plate disposed in a chamber body, one or more metal targets disposed in the chamber body, and a substrate support disposed below the gas distribution plate and the one or more targets.

Abstract: In one implementation, a sputtering showerhead assembly is provided. The sputtering showerhead assembly comprises a faceplate comprising a sputtering surface comprising a target material and a second surface opposing the sputtering surface, wherein a plurality of gas passages extend from the sputtering surface to the second surface. The sputtering showerhead assembly comprises further comprises a backing plate positioned adjacent to the second surface of the faceplate. The backing plate comprises a first surface and a second surface opposing the first surface. The sputtering showerhead assembly has a plenum defined by the first surface of the backing plate and the second surface of the faceplate. The sputtering showerhead assembly comprises further comprises one or more magnetrons positioned along the second surface of the backing plate.

Abstract: A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.

Abstract: A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.

Abstract: A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.

Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target.

Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target.

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

Abstract: In one implementation, a sputtering showerhead assembly is provided. The sputtering showerhead assembly comprises a faceplate comprising a sputtering surface comprising a target material and a second surface opposing the sputtering surface, wherein a plurality of gas passages extend from the sputtering surface to the second surface. The sputtering showerhead assembly comprises further comprises a backing plate positioned adjacent to the second surface of the faceplate. The backing plate comprises a first surface and a second surface opposing the first surface. The sputtering showerhead assembly has a plenum defined by the first surface of the backing plate and the second surface of the faceplate. The sputtering showerhead assembly comprises further comprises one or more magnetrons positioned along the second surface of the backing plate.