Patents by Inventor Prachi Mishra

Prachi Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12137081
    Abstract: A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 5, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Robin O. Hoel, Eric Peeters, Prithvi Shankar Yeyyadi Anantha, Aniruddha Periyapatna Nagendra, Shobhit Singhal, Ruchi Shankar, Prachi Mishra
  • Publication number: 20230253881
    Abstract: In some examples, a circuit includes sensing circuitry, a synchronization circuit, and a controller. The sensing circuitry is configured to provide a comparison result based on a comparison between a reference voltage and a feedback voltage. The synchronization circuit is configured to synchronize the comparison result into a clock domain to form a synchronous comparison result. The controller is configured to receive the synchronous comparison result, determine a predicted gate control signal based on the synchronous comparison result, determine a gate control signal based on the synchronous comparison result, provide the predicted gate control signal to the sensing circuitry as the feedback voltage, and provide the gate control signal for controlling a power converter.
    Type: Application
    Filed: October 14, 2022
    Publication date: August 10, 2023
    Inventors: Vineet KHURANA, Rinu MATHEW, Gayathri MURUGESH, Aniruddha PERIYAPATNA NAGENDRA, Prachi MISHRA
  • Patent number: 11650930
    Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: May 16, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Veeramanikandan Raju, Anand Kumar G, Prachi Mishra
  • Publication number: 20230091498
    Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Veeramanikandan RAJU, Anand Kumar G, Prachi MISHRA
  • Publication number: 20230076376
    Abstract: A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Inventors: Robin O. Hoel, Eric Peeters, Prithvi Shankar Yeyyadi Anantha, Aniruddha Periyapatna Nagendra, Shobhit Singhal, Ruchi Shankar, Prachi Mishra
  • Publication number: 20230050729
    Abstract: In described examples, a processor system includes a mailbox, a hardware security functional block (HSFB, also called a trusted agent herein), a processor, and a processor firewall. The HSFB includes a database configured to store at least one software context access rule. The processor executes multiple software contexts. The HSFB approves or denies an access request received from a debugging tool, via the mailbox, in response to the database and a software context identification (ID) included in the access request. The HSFB sends a message to the processor firewall indicating whether the access request is approved. The processor firewall determines whether to pass instructions to the processor for execution with respect to the identified software context in response to the message.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 16, 2023
    Inventors: Eric Thierry Jean Peeters, Gary Augustine Cooper, Robin Osa Hoel, Ruchi Shankar, Prachi Mishra