Abstract: A system and method of performing transaction level System on Chip (SoC) performance analysis includes obtaining a SoC description file including all intellectual property (IP) modules interconnected in a SoC via interconnects, calculating clock periods of the IP modules, calculating a greatest common divisor (GCD) of all the clock periods, receiving user-specified inputs that stimulate the SoC and generate a signal at an output of the SoC, gathering timing and interconnect statistics from the SoC, automatically generating a top level module based on the statistics, compiling the top level module and the components to generate an executable file, simulating a SoC system by running the executable file, and generating performance results from the simulated SoC system.