Patents by Inventor Prachi Shrivastava

Prachi Shrivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868236
    Abstract: A method for forming self aligned magnetic memory element pillars for Magnetic Random Access Memory. The method allows the magnetic memory element pillars to be arranged in staggered rows of memory elements at a pitch that is smaller than what is possible using photolithography alone. The method involves forming a spacer mask in the form of an array of connected rings arranged in a square pattern of non-staggered rows. A sacrificial mask material is deposited over the spacer mask and the spacer mask is then removed, leaving sacrificial mask material in the holes at the center of the rings and also in the spaces between the rings. A reactive ion processes is then performed to transfer the pattern of the sacrificial mask onto underlying hard mask layers. A material removal process can then be performed to define a plurality of memory element pillars.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: December 15, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Prachi Shrivastava, Yuan-Tung Chin
  • Patent number: 10811594
    Abstract: A method for fabricating an array of pillars. The method includes fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer. The method selects between subsequent electron beam patterning for the wafer and photolithography patterning for the wafer. For electron beam patterning, an electron beam lithography hard mask is deposited onto the metal stack, and an electron beam is used to pattern a first array of pillars into the electron beam lithography hard mask to produce a first resulting pillar array. For photolithography patterning, a photolithography hard mask is deposited onto the metal stack, and photolithography is used to pattern a second array of pillars into the photolithography hard mask to produce a second resulting pillar array. The first resulting pillar array is substantially the same as the second resulting pillar array.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 20, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Prachi Shrivastava, Daniel Liu, Yuan Tung Chin
  • Patent number: 10720573
    Abstract: A method for manufacturing a magnetic random access memory array at a density greater than would be possible using photolithography. A template is formed having a pattern that is configured to define a memory array. A block copolymer material is deposited onto the template and annealed to form narrow cylinders of ordered block copolymer material. A metal oxide is then diffused into the cylinders to form narrow metal oxide cylinders. The metal oxide cylinders can then be used as mask structures to pattern a hard mask layer. An ion milling process can then be performed to transfer the image of the patterned hard mask onto an underlying magnetic memory material to form an array having features sizes smaller than what would be possible using photolithography.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 21, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Elizabeth A. Dobisz, Prachi Shrivastava
  • Patent number: 10615337
    Abstract: A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 7, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Pradeep Manandhar, Prachi Shrivastava, Mustafa Pinarbasi, Thomas Boone
  • Patent number: 10516094
    Abstract: A method for a photolithographic fabricating process to define pillars having small pitch and pillar size. The method includes coating a hard mask layer of a wafer with a photoresist. The wafer is exposed with a first line pattern comprising a plurality of parallel lines in a first direction. The wafer is then exposed with a second line pattern comprising a plurality of parallel lines in a second direction orthogonal to the first direction. The wafer is then developed to remove areas of the photoresist that were exposed by the first line pattern and the second line pattern resulting in a plurality of pillars.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 24, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Prachi Shrivastava, Mustafa Pinarbasi, Thomas Boone
  • Publication number: 20190371997
    Abstract: A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.
    Type: Application
    Filed: April 18, 2019
    Publication date: December 5, 2019
    Inventors: Pradeep Manandhar, Prachi Shrivastava, Mustafa Pinarbasi, Thomas Boone
  • Patent number: 10411185
    Abstract: A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 10, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Pradeep Manandhar, Prachi Shrivastava, Mustafa Pinarbasi, Thomas Boone
  • Publication number: 20190207107
    Abstract: A method for forming self aligned magnetic memory element pillars for Magnetic Random Access Memory. The method allows the magnetic memory element pillars to be arranged in staggered rows of memory elements at a pitch that is smaller than what is possible using photolithography alone. The method involves forming a spacer mask in the form of an array of connected rings arranged in a square pattern of non-staggered rows. A sacrificial mask material is deposited over the spacer mask and the spacer mask is then removed, leaving sacrificial mask material in the holes at the center of the rings and also in the spaces between the rings. A reactive ion processes is then performed to transfer the pattern of the sacrificial mask onto underlying hard mask layers. A material removal process can then be performed to define a plurality of memory element pillars.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventors: Prachi Shrivastava, Yuan-Tung Chin
  • Publication number: 20190207082
    Abstract: A method for a photolithographic fabricating process to define pillars having small pitch and pillar size. The method includes coating a hard mask layer of a wafer with a photoresist. The wafer is exposed with a first line pattern comprising a plurality of parallel lines in a first direction. The wafer is then exposed with a second line pattern comprising a plurality of parallel lines in a second direction orthogonal to the first direction. The wafer is then developed to remove areas of the photoresist that were exposed by the first line pattern and the second line pattern resulting in a plurality of pillars.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Prachi Shrivastava, Mustafa Pinarbasi, Thomas Boone
  • Publication number: 20190207080
    Abstract: A method for fabricating an array of pillars. The method includes fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer. The method selects between subsequent electron beam patterning for the wafer and photolithography patterning for the wafer. For electron beam patterning, an electron beam lithography hard mask is deposited onto the metal stack, and an electron beam is used to pattern a first array of pillars into the electron beam lithography hard mask to produce a first resulting pillar array. For photolithography patterning, a photolithography hard mask is deposited onto the metal stack, and photolithography is used to pattern a second array of pillars into the photolithography hard mask to produce a second resulting pillar array. The first resulting pillar array is substantially the same as the second resulting pillar array.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Prachi Shrivastava, Daniel Liu, Yuan Tung Chin
  • Publication number: 20190207108
    Abstract: A method for manufacturing a magnetic random access memory array at a density greater than would be possible using photolithography. A template is formed having a pattern that is configured to define a memory array. A block copolymer material is deposited onto the template and annealed to form narrow cylinders of ordered block copolymer material. A metal oxide is then diffused into the cylinders to form narrow metal oxide cylinders. The metal oxide cylinders can then be used as mask structures to pattern a hard mask layer. An ion milling process can then be performed to transfer the image of the patterned hard mask onto an underlying magnetic memory material to form an array having features sizes smaller than what would be possible using photolithography.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventors: Elizabeth A. Dobisz, Prachi Shrivastava
  • Publication number: 20190207101
    Abstract: A method for fabricating an array of pillars. The method includes fabricating a plurality of lines of photoresist on a hard mask stack and depositing a spacer film on top of the plurality of lines of photoresist. The method further includes etching the spacer film to remove the spacer film from the top of the plurality of lines of photoresist and stripping the plurality of lines of photoresist to leave behind to spacer lines for each resist line. The method concludes with etching the spacer lines and the hard mask stack to yield an array of pillars.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Prachi Shrivastava, Yuan Tung Chin, Thomas Boone, Mustafa Pinarbasi
  • Patent number: 10312435
    Abstract: A method for manufacturing a magnetic random access memory array at a density greater than would be possible using photolithography. A hard mask material is deposited over a magnetic memory element material, and a chemical template layer such as brush or mat material is deposited over the hard mask. A mask structure is formed over the soluble polymer. The mask structure is configured with openings having a center to center spacing that is an integer multiple of a block copolymer material. The openings in the mask structure can be shrunk by depositing a spacer material. The chemical template layer is chemically patterned, such as by a quick plasma exposure and the mask is removed. A block copolymer material is then deposited over the chemical template and annealed to form block copolymer cylinders that are located over the patterned portions of the chemical template and between the patterned portions.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 4, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Elizabeth A. Dobisz, Prachi Shrivastava
  • Patent number: 10305031
    Abstract: A method for manufacturing a magnetic random access memory array at a density greater than would be possible using photolithography. The method involves patterning a chemical template material with patterned portions separated by a center to center distance that is substantially equal to a natural period of a block copolymer. A block copolymer material is then deposited and annealed to form self assembled cylinders that are located over the patterned regions of the chemical template and also over areas between the patterned regions. The chemical template layer can be patterned by depositing a first, preliminary block copolymer, over a mask structure and annealing the mask structure to form cylinders in the openings in the mask structure. The cylinders can be removed leaving openings, and a UV exposure can be performed to expose and treat portions of the chemical template layer that are exposed through the opening.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 28, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Elizabeth A. Dobisz, Prachi Shrivastava