Abstract: Systems and methods for converting an input analog signal to a digital representation thereof. A method includes determining an input analog signal voltage range of the input analog signal, and splitting the input analog signal voltage range into n+1 sub-ranges, n being a number of splits in the input analog signal voltage range. The method also includes assigning a respective N-bit coarse digital code i to each sub-range. The method also includes identifying the input analog signal with a corresponding sub-range, the corresponding sub-range having respective digital code i. A delta-sigma operation is performed on the input analog signal using upper and lower reference voltages of the corresponding sub-range that the input analog signal is identified with, to produce the digital representation.

Abstract: The application generally discloses systems and methods of generating a voltage waveform having an amplitude three times an input voltage amplitude using a plurality of low voltage (LV) triple well (TWL)N-type field effect devices. The method includes: receiving a first input voltage at a first input of a double switch charge transfer switch (CTS) circuit; applying a 2× kick voltage to a first capacitor coupled to a first portion of the double switch CTS circuit, the first capacitor configured to discharge a kick voltage to a source of a first LV TWL N-type field effect device; and applying a 1× kick voltage to a second capacitor coupled a second portion of the double switch CTS circuit, the second capacitor configured to discharge a kick voltage to a source of a second LV TWL N-type field effect device.

Abstract: An apparatus and method for detecting leakage current in a non-volatile memory array. A reference current is connected to a leakage detection circuit. A reference code is determined for the leakage detection circuit coupled to a switching circuit. The reference code establishes a leakage current threshold. The reference current is disconnected from the leakage detection circuit and the switching circuit. Next, the leakage detection circuit is connected to a set of word lines of a storage block of a non-volatile memory array by way of the switching circuit. A memory current is generated within the set of word lines. A leakage code is determined for the set of word lines representing leakage current from the word lines in response to the memory current. The leakage code is compared with the reference code. If the leakage code exceeds the reference code, the storage block is deemed unusable.

Abstract: A charge pump includes first and second multiplier stages including first and second capacitor in series with an input node, a final multiplier stage including an output capacitor in series with the second capacitor and an output node, and pre-charge circuitry. The pre-charge circuitry is configured to charge the output capacitor to a first level during an initial phase of a charging operation, wherein the first level is equal to a supply voltage of the data storage system, and decouple a charging path of the pre-charge circuitry from the output capacitor in response to the output capacitor being charged to the first level. The first and second multiplier stages are configured to increase the charge of the output capacitor to second and third levels higher than the first level during second and third phases of the charging operation.

Abstract: An apparatus and method for detecting leakage current in a non-volatile memory array. A reference current is connected to a leakage detection circuit. A reference code is determined for the leakage detection circuit coupled to a switching circuit. The reference code establishes a leakage current threshold. The reference current is disconnected from the leakage detection circuit and the switching circuit. Next, the leakage detection circuit is connected to a set of word lines of a storage block of a non-volatile memory array by way of the switching circuit. A memory current is generated within the set of word lines. A leakage code is determined for the set of word lines representing leakage current from the word lines in response to the memory current. The leakage code is compared with the reference code. If the leakage code exceeds the reference code, the storage block is deemed unusable.

Abstract: A circuit comprising 1) a master delay-locked loop comprising a phase detector for receiving a reference clock and generating an output, control logic for receiving the output from the phase detector and a delta delay input and generating a control output, a clock splitter for receiving the reference clock and generating differential clock output, a delay line for receiving the differential reference clock from the clock splitter and generating n phases of differential reference clock at output, a multiplexer for receiving the output from the delay line and the control logic output and generating a clock output, wherein the phase detector is for receiving the reference clock, and 2) a slave delay-locked loop for receiving the control logic output and a strobe input and generating a delay locked loop output.

Abstract: A circuit comprising 1) a master delay-locked loop comprising a phase detector for receiving a reference clock and generating an output, control logic for receiving the output from the phase detector and a delta delay input and generating a control output, a clock splitter for receiving the reference clock and generating differential clock output, a delay line for receiving the differential reference clock from the clock splitter and generating n phases of differential reference clock at output, a multiplexer for receiving the output from the delay line and the control logic output and generating a clock output, wherein the phase detector is for receiving the reference clock, and 2) a slave delay-locked loop for receiving the control logic output and a strobe input and generating a delay locked loop output.