Patents by Inventor Pradeep Batra
Pradeep Batra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7054771Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.Type: GrantFiled: February 28, 2005Date of Patent: May 30, 2006Assignee: Rambus, Inc.Inventors: Pradeep Batra, Rick A. Rutkowski
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Publication number: 20060015275Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.Type: ApplicationFiled: September 23, 2005Publication date: January 19, 2006Applicant: Rambus Inc.Inventors: Pradeep Batra, Rick Rutkowski
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Patent number: 6988044Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.Type: GrantFiled: April 8, 2003Date of Patent: January 17, 2006Assignee: Rambus Inc.Inventors: Pradeep Batra, Rick A. Rutkowski
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Patent number: 6954837Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage.Type: GrantFiled: April 12, 2004Date of Patent: October 11, 2005Assignee: Rambus Inc.Inventors: Steven C. Woo, Pradeep Batra
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Publication number: 20050146963Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.Type: ApplicationFiled: February 28, 2005Publication date: July 7, 2005Applicant: Rambus Inc.Inventors: Pradeep Batra, Rick Rutkowski
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Publication number: 20040193829Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage.Type: ApplicationFiled: April 12, 2004Publication date: September 30, 2004Inventors: Steven C. Woo, Pradeep Batra
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Patent number: 6742097Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage.Type: GrantFiled: July 30, 2001Date of Patent: May 25, 2004Assignee: Rambus Inc.Inventors: Steven C. Woo, Pradeep Batra
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Publication number: 20040034485Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.Type: ApplicationFiled: April 8, 2003Publication date: February 19, 2004Inventors: Pradeep Batra, Rick A. Rutkowski
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Patent number: 6546343Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.Type: GrantFiled: November 13, 2000Date of Patent: April 8, 2003Assignee: Rambus, Inc.Inventors: Pradeep Batra, Rick A. Rutkowski
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Publication number: 20030028711Abstract: Described herein is a system for operating memory at reduced power, based on whether the memory is actually in use. A memory controller receives notifications from an operating system or other computer program regarding which areas of physical memory are actually in use. The memory controller is responsive to the notifications to operate unused portions of memory at reduced power. In systems having refreshable memory, the memory controller omits refreshing for those memory rows that are not currently in use.Type: ApplicationFiled: July 30, 2001Publication date: February 6, 2003Inventors: Steven C. Woo, Pradeep Batra
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Publication number: 20030023825Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage.Type: ApplicationFiled: July 30, 2001Publication date: January 30, 2003Inventors: Steven C. Woo, Pradeep Batra
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Patent number: 6232796Abstract: A method of detecting two bits of data transmitted with a single clock edge includes the step of assessing the value of a first data bit and a second data bit transmitted with a single clock edge to generate a first output bit indicative of the value of said first data bit. The assessing step may be implemented by integrating the first data bit and the second data bit, or by identifying signal transitions between the first data bit and the second data bit. The second output bit is produced by simply passing the second data bit.Type: GrantFiled: July 21, 1999Date of Patent: May 15, 2001Assignee: Rambus IncorporatedInventors: Pradeep Batra, Stefanos Sidiropoulos
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Patent number: 6151239Abstract: An apparatus and method for storing data in a memory. Mask information is embedded in a data packet and used to indicate memory locations at which data values in the data packet are to be stored.Type: GrantFiled: November 15, 1999Date of Patent: November 21, 2000Assignee: Rambus Inc.Inventor: Pradeep Batra
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Patent number: 6122189Abstract: An apparatus and method for storing data in a memory. Mask information is embedded in a data packet and used to indicate memory locations at which data values in the data packet are to be stored.Type: GrantFiled: October 2, 1998Date of Patent: September 19, 2000Assignee: Rambus Inc.Inventor: Pradeep Batra
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Patent number: 6009487Abstract: In a system comprising a current controlling device and a plurality of signal lines coupled to the current controlling device, wherein the current controlling device has an output driver including a register, an improved method for setting a current of the output driver for at least one of the plurality of signal lines. The improved method determines a reference register-setting for the register of the current controlling device. The reference register-setting corresponds to a reference voltage for at least one of the plurality of signal lines. A target register-setting is then determined for the register based on the reference register-setting. The target register-setting corresponds to a target voltage for at least one of the plurality of signal lines, wherein the target voltage produces an appropriate swing about the reference voltage. An operational register-setting is then determined for the register based on the target register-setting.Type: GrantFiled: May 31, 1996Date of Patent: December 28, 1999Assignee: Rambus Inc.Inventors: Paul Gregory Davis, Pradeep Batra, John B. Dillon, Karnamadakala Krishnamohan, James A. Gasbarro
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Patent number: 5249133Abstract: The present invention takes advantage of the hierarchical nature of the design to perform a hierarchical comparison on as many blocks and sub-blocks which can be matched between the layout and the logic design. Because the internal connections were previously verified when the first occurrence of the block was compared, repetition of lengthy comparisons of multiple occurrences of the same blocks in the designs is avoided and subsequent comparisons are performed simply by comparing the input and output connections to the block.Type: GrantFiled: April 10, 1991Date of Patent: September 28, 1993Assignee: Sun Microsystems, Inc.Inventor: Pradeep Batra