Patents by Inventor Pradeep Fernando

Pradeep Fernando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Speeding up transactions in non-volatile memory using hardware transactional memory
    Patent number: 10430186
    Abstract: The disclosure provides an approach for atomically executing computer instructions by a CPU of a computing device comprising non-volatile memory, the CPU configured to implement hardware transactional memory (HTM). The approach generally includes reading an instruction within a section of code designated as an HTM transaction, determining whether the instruction causes a data conflict with another thread, and copying cache lines from memory into a cache of the CPU. The approach further includes marking the copied cache lines as transactional, processing the instruction to create a persistent log within non-volatile memory, and unmarking the copied cache lines from transactional, to non-transactional.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: October 1, 2019
    Assignee: VMware, Inc.
    Inventors: Irina Calciu, Jayneel Gandhi, Pradeep Fernando, Aasheesh Kolli
  • Fault tolerance in shared memory
    Patent number: 10416931
    Abstract: Examples herein involve fault tolerance in a shared memory. In examples herein, a metadata store of a shared memory indicating versions of data partitions of a resilient distributed dataset and a valid flag for the partitions of the resilient distributed dataset are used to achieve fault tolerance and/or recover from faults in the share memory.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 17, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Pradeep Fernando, Mijung Kim, Haris Volos, Jun Li
  • SPEEDING UP TRANSACTIONS IN NON-VOLATILE MEMORY USING HARDWARE TRANSACTIONAL MEMORY
    Publication number: 20190129716
    Abstract: The disclosure provides an approach for atomically executing computer instructions by a CPU of a computing device comprising non-volatile memory, the CPU configured to implement hardware transactional memory (HTM). The approach generally includes reading an instruction within a section of code designated as an HTM transaction, determining whether the instruction causes a data conflict with another thread, and copying cache lines from memory into a cache of the CPU. The approach further includes marking the copied cache lines as transactional, processing the instruction to create a persistent log within non-volatile memory, and unmarking the copied cache lines from transactional, to non-transactional.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Irina CALCIU, Jayneel GANDHI, Pradeep FERNANDO, Aasheesh KOLLI
  • FAULT TOLERANCE IN SHARED MEMORY
    Publication number: 20180095834
    Abstract: Examples herein involve fault tolerance in a shared memory. In examples herein, a metadata store of a shared memory indicating versions of data partitions of a resilient distributed dataset and a valid flag for the partitions of the resilient distributed dataset are used to achieve fault tolerance and/or recover from faults in the share memory.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Pradeep Fernando, Mijung Kim, Haris Volos, Jun Li