Patents by Inventor Pradeep Ganesan Nagarajan

Pradeep Ganesan Nagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testing hierarchical address translation with context switching and overwritten table definition data
    Patent number: 11138126
    Abstract: Data processing apparatus comprises one or more processing elements to execute processing instructions; address translation circuitry to perform address translations between a virtual address space and a physical address space, the address translations being defined by a current hierarchical set of address translation tables selected from two or more hierarchical sets of address translation tables, the address translation circuitry being responsive to current table definition data providing at least a pointer to a memory location of the current hierarchical set of address translation tables; the one or more processing elements being configured to overwrite the current table definition data with second table definition data providing at least a pointer to a memory location of a second, different, hierarchical set of address translation tables of the two or more hierarchical sets of address translation tables; the one or more processing elements being configured to execute test instructions requiring address tr
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: October 5, 2021
    Assignee: Arm Limited
    Inventor: Pradeep Ganesan Nagarajan
  • DATA PROCESSING
    Publication number: 20200026660
    Abstract: Data processing apparatus comprises one or more processing elements to execute processing instructions; address translation circuitry to perform address translations between a virtual address space and a physical address space, the address translations being defined by a current hierarchical set of address translation tables selected from two or more hierarchical sets of address translation tables, the address translation circuitry being responsive to current table definition data providing at least a pointer to a memory location of the current hierarchical set of address translation tables; the one or more processing elements being configured to overwrite the current table definition data with second table definition data providing at least a pointer to a memory location of a second, different, hierarchical set of address translation tables of the two or more hierarchical sets of address translation tables; the one or more processing elements being configured to execute test instructions requiring address tr
    Type: Application
    Filed: June 24, 2019
    Publication date: January 23, 2020
    Inventor: Pradeep Ganesan Nagarajan