Patents by Inventor Pradeep Goyal
Pradeep Goyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250071026Abstract: A system and method of simulating an effect on a network in response to a network-related event. The method can include receiving data with respect to a plurality of nodes within a network and generating a network graph with respect to each of the nodes within the network. In addition, the method can include calculating a first value based on network traffic with respect to each of the nodes based on the received data and calculating a second value based on performance with respect to each of the nodes based on the received data. Further, the method can include updating the network graph by applying the calculated first value and second value and identifying, from the updated network graph, one or more nodes from the plurality of nodes that are susceptible to an error or outage within the network.Type: ApplicationFiled: August 3, 2022Publication date: February 27, 2025Applicant: RAKUTEN MOBILE, INCInventors: Ahmed ABDELAZIZ, Ziya AKHUNDOV, Ahmed TASNIM, Arun GOYAL, Pradeep KUMAR
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Patent number: 12231353Abstract: A fabric control protocol is described for use within a data center in which a switch fabric provides full mesh interconnectivity such that any of the servers may communicate packet data for a given packet flow to any other of the servers using any of a number of parallel data paths within the data center switch fabric. The fabric control protocol enables spraying of individual packets for a given packet flow across some or all of the multiple parallel data paths in the data center switch fabric and, optionally, reordering of the packets for delivery to the destination. The fabric control protocol may provide end-to-end bandwidth scaling and flow fairness within a single tunnel based on endpoint-controlled requests and grants for flows. In some examples, the fabric control protocol packet structure is carried over an underlying protocol, such as the User Datagram Protocol (UDP).Type: GrantFiled: January 28, 2020Date of Patent: February 18, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Deepak Goel, Narendra Jayawant Gathoo, Philip A Thomas, Srihari Raju Vegesna, Pradeep Sindhu, Wael Noureddine, Robert William Bowdidge, Ayaskant Pani, Gopesh Goyal
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Patent number: 12212495Abstract: A fabric control protocol (FCP) is a data transmission protocol that enables spraying of individual packets for a given packet flow across a data center from an ingress interface of the source data processing unit (DPU) across a plurality of parallel data paths of a logical tunnel in the network fabric to the egress interface of the destination DPU. The FCP has congestion control mechanisms used to determine a degree of congestion at the egress interface of the destination DPU and to modify a send window size at the source DPU based on the degree of congestion. Reliable FCP (rFCP) extensions provide reliability enhancements and improved failure resilience within the data center. The rFCP extensions provide an unsolicited mode for low latency operation with enhanced reliability mechanisms. The rFCP extensions provide failure resilience mechanisms to identify and avoid failed paths among multiple parallel data paths within the logical tunnel.Type: GrantFiled: June 9, 2021Date of Patent: January 28, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Srihari Raju Vegesna, Narendra Jayawant Gathoo, Pradeep Sindhu, Jean-Marc Frailong, Gopesh Goyal, Suresh Vemula, John David Huber, Chetan Ambalal Shah
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Patent number: 10380301Abstract: The present disclosure relates to a method for waveform based debugging in a formal verification of an integrated circuit. The method may include receiving, using at least one processor, an electronic circuit design and partitioning a cone of influence for a cover property of the electronic circuit design into design logic and property logic. The method may further include applying an X-value to all inputs associated with the cone of influence and performing an X-simulation until a fixed point is reached. The method may also include identifying a non-X node and providing a path of X-diffusion at a property output.Type: GrantFiled: March 17, 2017Date of Patent: August 13, 2019Assignee: Cadence Design Systems, Inc.Inventors: Pradeep Goyal, Mudit Sharma
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Patent number: 10176286Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. The method may include receiving, using a processor, an electronic design having a plurality of loops and removing a section of each of the plurality of loops. The method may further include obtaining an input/output net for each of the plurality of loops and generating a copy of at least a portion of the electronic design. The method may include connecting all inputs except a loop cut input net associated with the removed section and analyzing a loop output net using formal verification.Type: GrantFiled: March 17, 2017Date of Patent: January 8, 2019Assignee: Cadence Design Systems, Inc.Inventors: Pradeep Goyal, Ravindra Kumar
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Patent number: 10108767Abstract: Disclosed are methods, systems, and articles of manufacture for implementing deadlock detection with formal verification techniques in an electronic design. These techniques identify one or more inputs that include at least an initial state of an electronic design and identify at least one deadlock candidate by sweeping at least a portion of a state space of the electronic design with formal verification techniques. These techniques then determine whether the at least one deadlock candidate is a real deadlock by using a second formal search with the formal verification techniques.Type: GrantFiled: September 30, 2016Date of Patent: October 23, 2018Assignee: Cadence Design Systems, Inc.Inventors: Victor Markus Purri, Michael Dennis Pedneau, Lars Lundgren, Pradeep Goyal
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Patent number: 10031990Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. The method may include receiving, using a processor, an electronic design at a verification environment and generating a symbolic constant for use with the verification environment. The method may further include identifying a plurality of X sources associated with the verification environment and modifying the plurality of X sources based upon, at least in part, the symbolic constant. The method may also include running a first target node and if the first target node is proven, run at least one additional target node until all target nodes are proven.Type: GrantFiled: September 28, 2016Date of Patent: July 24, 2018Assignee: Cadence Design Systems, Inc.Inventors: Pradeep Goyal, Deepak Yadav, Jasmeet Singh Narula
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Patent number: 9873185Abstract: A system and process for rapid and uniform curing of grinding wheels (2) to obtain grinding wheels (2) with better durability, at 180-220° C. deploying microwave energy at 800-5000 MHz in which closely fitting green wheel sample holders (1) are made of carbon bearing microwave susceptor materials such as graphite, silicon carbide with tiny holes on the surface. These sample holders (1) help in maintaining the shape and geometry of the final wheels (2) after curing and reduce energy consumption. The performance of the grinding wheels (2) cured by this process is better than those cured by presently used process employing steel plate sample holders of the present state-of-art.Type: GrantFiled: July 17, 2013Date of Patent: January 23, 2018Assignee: Pradeep Metals LimitedInventors: Pradeep Goyal, Shivanand Borkar, Ritesh Jaiswal
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Publication number: 20150165594Abstract: A system and process for rapid and uniform curing of grinding wheels (2) to obtain grinding wheels (2) with better durability, at 180-220° C. deploying microwave energy at 800-5000 MHz in which closely fitting green wheel sample holders (1) are made of carbon bearing microwave susceptor materials such as graphite, silicon carbide with tiny holes on the surface. These sample holders (1) help in maintaining the shape and geometry of the final wheels (2) after curing and reduce energy consumption. The performance of the grinding wheels (2) cured by this process is better than those cured by presently used process employing steel plate sample holders of the present state-of-art.Type: ApplicationFiled: July 17, 2013Publication date: June 18, 2015Applicant: Pradeep Metals LimitedInventors: Pradeep Goyal, Shivanand Borkar, Ritesh Jaiswal
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Patent number: 8990746Abstract: The present disclosure relates to a method for formal verification of an integrated circuit design. The method may include providing an electronic design associated with the integrated circuit. The method may further include generating one or more faults in a cone of influence of an assertion and placing a constraint configured to model an original design for the one or more faults. The method may also include initiating formal verification on the electronic design while ignoring all electronic design constraints. The method may further include determining if the assertion is passing, wherein determining includes activating an original design for a subset of faults. If the assertion is passing, the method may include activating a single fault from the subset, determining if the assertion is passing and if the assertion does pass, deleting the single fault from the subset.Type: GrantFiled: March 26, 2014Date of Patent: March 24, 2015Assignee: Cadence Design Systems, Inc.Inventors: Pradeep Goyal, Alok Jain
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Patent number: 8910099Abstract: The present disclosure relates to a method for debugging in the formal verification of an integrated circuit design. The method may include providing, via a computing device, an electronic design associated with the integrated circuit. Embodiments may further include splitting one or more nets in a cone of influence of a target associated with the electronic design. For each split net, embodiments may include placing a constraint that re-joins the net. Embodiments may also include identifying a local region of the electronic design for which the target is unreachable. During formal verification, embodiments may include ignoring all constraints associated with the local region of the electronic design.Type: GrantFiled: March 5, 2014Date of Patent: December 9, 2014Assignee: Cadence Design Systems, Inc.Inventors: Pradeep Goyal, Alok Jain
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Patent number: 8612905Abstract: A method and apparatus for producing a vacuity detection report to reduce false positive verification results for digital circuits provided. In an exemplary embodiment, a design description of the digital design is generated. From the design description, a vacuity detection problem is derived by introducing an assertion into the design description. By introducing an assertion into the design description, the vacuity detection problem is solvable by formal assertion based verification engines. A verification engine is then used to solve the vacuity detection problem and produce a vacuity detection report. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.Type: GrantFiled: January 11, 2008Date of Patent: December 17, 2013Assignee: Cadence Design Systems, Inc.Inventors: Pradeep Goyal, Alok Jain, Manu Chopra, Anurag Gupta, Deepak Yadav
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Patent number: 8316332Abstract: The present disclosure relates to a method for minimizing constraints in the formal verification of an integrated circuit design. The method may include obtaining an unisolated list of constraints initially comprising all known constraints for the integrated circuit design and obtaining an isolated list of constraints initially comprising none of the known constraints. The method may further include attempting to prove an assertion without the known constraints and determining if the assertion is valid. The method may further include updating the isolated list of constraints.Type: GrantFiled: July 7, 2010Date of Patent: November 20, 2012Assignee: Cadence Design Systems, Inc.Inventors: Pradeep Goyal, Alok Jain