Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-? dielectric layer after the annealing process (in dipole last processes).

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular, and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers that are protected from material loss during removal of a middle sacrificial layer. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a middle sacrificial layer on a top surface of the first hGAA structure, the middle sacrificial layer comprising silicon germanium (SiGe); and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise silicon germanium (SiGe).

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

Abstract: A semiconductor structure includes a first common metal gate, a second common metal gate, a bottom field effect transistor (FET) module, the bottom FET module including a pair of bottom common source/drain (S/D) contacts electrically connected to each other through the first common metal gate in a first direction via first bottom S/D epitaxial (epi) regions, and through the second common metal gate in the first direction, and a top FET module stacked on the bottom FET module in a second direction that is orthogonal to the first direction, the top FET module including a top common S/D contact, a first top S/D contact electrically connected to the top common S/D contact through the first common metal gate in the first direction, and a second top S/D contact electrically connected to the top common S/D contact through the second common metal gate in the first direction.

Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-K dielectric layer after the annealing process (in dipole last processes).

Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.

Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

Abstract: Embodiments of the disclosure relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in a substrate, as well as control of the effects of OPD and the effects that the modifications made to the substrate to correct for the OPD have on subsequent substrate processing operations performed on the substrate. The present embodiments employ novel techniques to reduce the OPD in a substrate without adding or modifying portions of the substrate that will create issues in subsequent substrate fabrication processes.

Abstract: Embodiments of the disclosure relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in a substrate, as well as control of the effects of OPD and the effects that the modifications made to the substrate to correct for the OPD have on subsequent substrate processing operations performed on the substrate. The present embodiments employ novel techniques to reduce the OPD in a substrate without adding or modifying portions of the substrate that will create issues in subsequent substrate fabrication processes.

Abstract: Embodiments of the disclosure include an apparatus and method of forming an improved memory device. In some embodiments, the apparatus generally includes, for example, a plurality of alternating layers formed over a surface of a substrate including a plurality of word line layers with gate regions and a plurality of inter-word line dielectric layers; a channel; and an ONO layer stack disposed between the gate regions and the channel. The embodiments of the present disclosure may include at least one of: word line layers with gate regions that have sidewalls that have a reverse dome shape, sacrificial layers disposed between the word line layers and the inter-word line dielectric layers, or top and bottom dielectric layers deposited on top and bottom portions of the word line layers. Embodiments of the disclosure described herein may allow for the electric field of the gate regions of a memory device to be modified.

Abstract: A three-dimensional (3D) NAND memory structure may include alternating layers of materials arranged in a vertical stack on a silicon substrate, such as alternating oxide and nitride layers. The alternating nitride layers may later be removed, and the recesses may be filled with a conductive material to form word lines for the memory array. To avoid pinching off these recesses with silicon byproducts from a traditional wet etch, a dry etch may be instead be used to remove the nitrite layers. To protect the silicon substrate, a first insulating layer may be deposited at the bottom of the slit to cover the exposed silicon substrate before performing the dry etch. After applying a second insulating layer to cover the alternating oxide/nitride layers, a directional etch may punch through both insulating layers to again expose the silicon substrate before applying a solid material fill in the slit.

Abstract: A three-dimensional (3D) NAND memory structure may include material layers arranged in a vertical stack including alternating horizontal insulating layers and wordline layers. The material layers may be etched to form a landing pad. A vertical wordline may extend through one or more of the horizontal wordline layers beneath the landing pad. The vertical wordline may be conductively connected to a top horizontal wordline, and the vertical wordline may be insulated from any of the horizontal wordlines that the vertical wordline extends through beneath the top horizontal wordline. A liner may also be formed over a top horizontal wordline at the landing pad.

Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.

Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

Abstract: Provided are methods of reducing the stress of a semiconductor wafer. A wafer map of a free-standing wafer is created using metrology tools. The wafer map is then converted into a power spectral density (PSD) using a spatial frequency scale. The fundamental component of bow is then compensated with a uniform film, e.g., silicon nitride (SiN), deposited on the back side of the wafer.