Patents by Inventor Pradeep K. Subrahmanyan
Pradeep K. Subrahmanyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105641Abstract: Embodiments of the disclosure relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in a substrate, as well as control of the effects of OPD and the effects that the modifications made to the substrate to correct for the OPD have on subsequent substrate processing operations performed on the substrate. The present embodiments employ novel techniques to reduce the OPD in a substrate without adding or modifying portions of the substrate that will create issues in subsequent substrate fabrication processes.Type: ApplicationFiled: September 6, 2023Publication date: March 28, 2024Inventor: Pradeep K. SUBRAHMANYAN
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Publication number: 20240103385Abstract: Embodiments of the disclosure relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in a substrate, as well as control of the effects of OPD and the effects that the modifications made to the substrate to correct for the OPD have on subsequent substrate processing operations performed on the substrate. The present embodiments employ novel techniques to reduce the OPD in a substrate without adding or modifying portions of the substrate that will create issues in subsequent substrate fabrication processes.Type: ApplicationFiled: March 21, 2023Publication date: March 28, 2024Inventor: Pradeep K. SUBRAHMANYAN
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Publication number: 20240081063Abstract: Embodiments of the disclosure include an apparatus and method of forming an improved memory device. In some embodiments, the apparatus generally includes, for example, a plurality of alternating layers formed over a surface of a substrate including a plurality of word line layers with gate regions and a plurality of inter-word line dielectric layers; a channel; and an ONO layer stack disposed between the gate regions and the channel. The embodiments of the present disclosure may include at least one of: word line layers with gate regions that have sidewalls that have a reverse dome shape, sacrificial layers disposed between the word line layers and the inter-word line dielectric layers, or top and bottom dielectric layers deposited on top and bottom portions of the word line layers. Embodiments of the disclosure described herein may allow for the electric field of the gate regions of a memory device to be modified.Type: ApplicationFiled: August 10, 2023Publication date: March 7, 2024Inventors: Milan PESIC, Pradeep K. SUBRAHMANYAN
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Publication number: 20240055269Abstract: A three-dimensional (3D) NAND memory structure may include alternating layers of materials arranged in a vertical stack on a silicon substrate, such as alternating oxide and nitride layers. The alternating nitride layers may later be removed, and the recesses may be filled with a conductive material to form word lines for the memory array. To avoid pinching off these recesses with silicon byproducts from a traditional wet etch, a dry etch may be instead be used to remove the nitrite layers. To protect the silicon substrate, a first insulating layer may be deposited at the bottom of the slit to cover the exposed silicon substrate before performing the dry etch. After applying a second insulating layer to cover the alternating oxide/nitride layers, a directional etch may punch through both insulating layers to again expose the silicon substrate before applying a solid material fill in the slit.Type: ApplicationFiled: August 11, 2022Publication date: February 15, 2024Applicant: Applied Materials, Inc.Inventors: Sankuei Lin, Changwoo Sun, Pradeep K. Subrahmanyan
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Publication number: 20240046966Abstract: A three-dimensional (3D) NAND memory structure may include material layers arranged in a vertical stack including alternating horizontal insulating layers and wordline layers. The material layers may be etched to form a landing pad. A vertical wordline may extend through one or more of the horizontal wordline layers beneath the landing pad. The vertical wordline may be conductively connected to a top horizontal wordline, and the vertical wordline may be insulated from any of the horizontal wordlines that the vertical wordline extends through beneath the top horizontal wordline. A liner may also be formed over a top horizontal wordline at the landing pad.Type: ApplicationFiled: August 8, 2023Publication date: February 8, 2024Applicant: Applied Materials, Inc.Inventors: Hsiang Yu Lee, Pradeep K. Subrahmanyan, Takaya Matsushita, Changwoo Sun
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Publication number: 20230413569Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.Type: ApplicationFiled: May 18, 2023Publication date: December 21, 2023Applicant: Applied Materials, Inc.Inventors: Hsiang Yu Lee, Pradeep K. Subrahmanyan
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Publication number: 20230380170Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.Type: ApplicationFiled: May 18, 2023Publication date: November 23, 2023Applicant: Applied Materials, Inc.Inventors: Hsiang Yu Lee, Pradeep K. Subrahmanyan
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Publication number: 20230037719Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.Type: ApplicationFiled: November 20, 2021Publication date: February 9, 2023Applicant: Applied Materials, Inc.Inventors: SanKuei Lin, Pradeep K. Subrahmanyan
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Publication number: 20220384469Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.Type: ApplicationFiled: May 25, 2021Publication date: December 1, 2022Applicant: Applied Materials, Inc.Inventors: Yong Yang, Jacqueline S. Wrench, Yixiong Yang, Pradeep K. Subrahmanyan, Srinivas Gandikota
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Publication number: 20220344282Abstract: Provided are methods of reducing the stress of a semiconductor wafer. A wafer map of a free-standing wafer is created using metrology tools. The wafer map is then converted into a power spectral density (PSD) using a spatial frequency scale. The fundamental component of bow is then compensated with a uniform film, e.g., silicon nitride (SiN), deposited on the back side of the wafer.Type: ApplicationFiled: April 27, 2022Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Pradeep K. Subrahmanyan, Sean S. Kang, Sony Varghese
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Patent number: 7372660Abstract: A disc drive controller circuit for an actuator receives reference data indicating a desired actuator position “?d”, error data indicating a difference “e” between the desired actuator position and a sensed actuator position “?”, and adaptive parameter data “”. The controller circuit calculates a circuit output “u” that drives the actuator. The controller circuit derives the circuit output “u” according to a formula: A ^ ? ( ? ¨ d + 2 ? ? ? ? ? e . + ? 2 ? e ) + k ? ( e . + 2 ? ? ? ? ? e + ? 2 ? ? 0 t ? e ? ? ? ? ) in which “?” is a controller zero value and “k” is a controller gain value and “t” is time. The adaptive parameter  is updated in general accordance with the formula: Â(k)=e1e2?t+Â(k?1).Type: GrantFiled: January 23, 2001Date of Patent: May 13, 2008Assignee: Seagate Technology LLCInventor: Pradeep K. Subrahmanyan
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Patent number: 6898042Abstract: A microactuator comprises a stator, a rotor and an operator coupling the rotor to the stator. The operator comprises a four-block magnet array supported by either the stator or rotor, and first and second coils supported by the other of the stator or rotor. Current in one coil alters magnetic flux linkage to move the rotor along a first axis. Current in the other coil alters magnetic flux linkage to move the rotor along a second axis orthogonal to the first axis. The microactuator is applied to the slider of a disc drive to position the head at a selected flying distance adjacent the disc medium, and to position the head relative to a track on the medium.Type: GrantFiled: May 6, 2002Date of Patent: May 24, 2005Assignee: Seagate Technology LLCInventor: Pradeep K. Subrahmanyan
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Publication number: 20020181140Abstract: A microactuator comprises a stator, a rotor and an operator coupling the rotor to the stator. The operator comprises a four-block magnet array supported by either the stator or rotor, and first and second coils supported by the other of the stator or rotor. Current in one coil alters magnetic flux linkage to move the rotor along a first axis. Current in the other coil alters magnetic flux linkage to move the rotor along a second axis orthogonal to the first axis. The microactuator is applied to the slider of a disc drive to position the head at a selected flying distance adjacent the disc medium, and to position the head relative to a track on the medium.Type: ApplicationFiled: May 6, 2002Publication date: December 5, 2002Inventor: Pradeep K. Subrahmanyan