Patents by Inventor Pradeep Kiran Sarvepalli

Pradeep Kiran Sarvepalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6983032
    Abstract: The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: January 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Fernando A. Mujica, Udayan Dasgupta, Sandeep Kesrimal Oswal, Murtaza Ali, Pradeep Kiran Sarvepalli, Prakash Easwaran, Diptendra Narayan Basu
  • Publication number: 20030043945
    Abstract: The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).
    Type: Application
    Filed: August 28, 2001
    Publication date: March 6, 2003
    Inventors: Fernando A. Mujica, Udayan Dasgupta, Sandeep Kesrimal Oswal, Murtaza Ali, Pradeep Kiran Sarvepalli, Prakash Easwaran, Diptendra Narayan Basu