Patents by Inventor Pradeep Kumar Bajpai
Pradeep Kumar Bajpai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11747885Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: GrantFiled: November 17, 2022Date of Patent: September 5, 2023Assignee: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak
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Patent number: 11728930Abstract: Disclosed are techniques to regenerate SYNC bits of a High-Speed data packet lost by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may lose some SYNC bits at the beginning of the SYNC pattern. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. If the end of the SYNC is read before a programmable number of SYNC bits have been transmitted, the repeater/hub generates additional SYNC bits for transmission until the programmable number of SYNC bits are transmitted. The repeater/hub then resumes transmitting the rest of the High-Speed data packet starting from the payload.Type: GrantFiled: December 7, 2022Date of Patent: August 15, 2023Assignee: Cypress Semiconductor CorporationInventors: Godwin Gerald Arulappan, Pradeep Kumar Bajpai
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Publication number: 20230099199Abstract: Disclosed are techniques to regenerate SYNC bits of a High-Speed data packet lost by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may lose some SYNC bits at the beginning of the SYNC pattern. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. If the end of the SYNC is read before a programmable number of SYNC bits have been transmitted, the repeater/hub generates additional SYNC bits for transmission until the programmable number of SYNC bits are transmitted. The repeater/hub then resumes transmitting the rest of the High-Speed data packet starting from the payload.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Applicant: Cypress Semiconductor CorporationInventors: Godwin Gerald ARULAPPAN, Pradeep Kumar BAJPAI
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Publication number: 20230081229Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: ApplicationFiled: November 17, 2022Publication date: March 16, 2023Applicant: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak
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Patent number: 11528095Abstract: Disclosed are techniques for removing dribble bits following the end-of-packet (EOP) of a High-Speed data packet inserted by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may include dribble bits inserted by the PHY after the EOP. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. The repeater/hub monitors the EOP. When the EOP is detected, the repeater/hub prevents transmission of the dribble bits of the recovered bit stream following the EOP from the second port, eliminating the intended receiver of the High-Speed data packet from the complexity of dealing with dribble bits.Type: GrantFiled: December 11, 2020Date of Patent: December 13, 2022Assignee: Cypress Semiconductor CorporationInventors: Godwin Gerald Arulappan, Pradeep Kumar Bajpai
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Patent number: 11513584Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: GrantFiled: March 4, 2021Date of Patent: November 29, 2022Assignee: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak
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Publication number: 20220283624Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Applicant: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak
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Publication number: 20220190960Abstract: Disclosed are techniques for removing dribble bits following the end-of-packet (EOP) of a High-Speed data packet inserted by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may include dribble bits inserted by the PHY after the EOP. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. The repeater/hub monitors the EOP. When the EOP is detected, the repeater/hub prevents transmission of the dribble bits of the recovered bit stream following the EOP from the second port, eliminating the intended receiver of the High-Speed data packet from the complexity of dealing with dribble bits.Type: ApplicationFiled: December 11, 2020Publication date: June 16, 2022Applicant: Cypress Semiconductor CorporationInventors: Godwin Gerald Arulappan, Pradeep Kumar Bajpai
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Patent number: 11262827Abstract: In an example embodiment, a Universal Serial Bus (USB) Type-C cable comprises a USB Type-C connector and an IC controller coupled thereto. The IC controller comprises a terminal coupled to a VCONN line of the USB Type-C cable, a transistor coupled between the terminal and an internal power supply of the IC controller, a resistive element coupled between the terminal and a control terminal of the transistor, and control logic. The IC controller is to: power on the transistor from a voltage, received at the terminal, falling across the resistive element; power on the internal power supply in response to the voltage being passed through the transistor; power up the IC controller in response to powering on the internal power supply; and operate the control logic to fully power on the transistor, and thus enter an active mode of the IC controller.Type: GrantFiled: July 1, 2020Date of Patent: March 1, 2022Assignee: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
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Publication number: 20200409440Abstract: In an example embodiment, a Universal Serial Bus (USB) Type-C cable comprises a USB Type-C connector and an IC controller coupled thereto. The IC controller comprises a terminal coupled to a VCONN line of the USB Type-C cable, a transistor coupled between the terminal and an internal power supply of the IC controller, a resistive element coupled between the terminal and a control terminal of the transistor, and control logic. The IC controller is to: power on the transistor from a voltage, received at the terminal, falling across the resistive element power on the internal power supply in response to the voltage being passed through the transistor; power up the IC controller in response to powering on the internal power supply; and operate the control logic to fully power on the transistor, and thus enter an active mode of the IC controller.Type: ApplicationFiled: July 1, 2020Publication date: December 31, 2020Applicant: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
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Patent number: 10719112Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.Type: GrantFiled: April 12, 2019Date of Patent: July 21, 2020Assignee: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
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Publication number: 20190332150Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.Type: ApplicationFiled: April 12, 2019Publication date: October 31, 2019Applicant: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
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Patent number: 10317969Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.Type: GrantFiled: September 6, 2018Date of Patent: June 11, 2019Assignee: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
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Publication number: 20180081697Abstract: Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with USB 3.0. The host device comprises a reduced functionality USB host controller configured to perform a set of one or more preprogrammed functions from the USB 3.0 specification, and a universal asynchronous receiver and transmitter (UART) configured to sample USB response data received from the peripheral device over the bus.Type: ApplicationFiled: August 24, 2017Publication date: March 22, 2018Applicant: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Robert G. Rundell
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Publication number: 20180011718Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.Type: ApplicationFiled: July 20, 2017Publication date: January 11, 2018Applicant: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Robert G. Rundell, Syed Babar Raza
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Patent number: 9804858Abstract: Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with USB 3.0. The host device comprises a reduced functionality USB host controller configured to perform a set of one or more preprogrammed functions from the USB 3.0 specification, and a universal asynchronous receiver and transmitter (UART) configured to sample USB response data received from the peripheral device over the bus.Type: GrantFiled: September 27, 2016Date of Patent: October 31, 2017Assignee: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Robert G. Rundell
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Patent number: 9766901Abstract: Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with USB 3.0. The host device comprises a reduced functionality USB host controller configured to perform a set of one or more preprogrammed functions from the USB 3.0 specification, and a universal asynchronous receiver and transmitter (UART) configured to sample USB response data received from the peripheral device over the bus.Type: GrantFiled: September 27, 2016Date of Patent: September 19, 2017Assignee: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Robert G. Rundell
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Patent number: 9590441Abstract: Techniques for controlling the charging of portable devices are described herein. In an example embodiment, an apparatus comprises a controller coupled to a Universal Serial Bus (USB) port that is configured as a dedicated charging port (DCP). The controller is configured to detect whether a battery-charging (BC) compliant device or a BC non-compliant device is attached to the USB port. When a BC compliant device is detected, the controller controls the charging of the BC compliant device (e.g., by providing a maximum of 1.5 A of charging current). When a BC non-compliant device is detected, the controller controls the charging of the BC non-compliant device by providing a higher (e.g., up to 2.4 A) charging current.Type: GrantFiled: June 25, 2015Date of Patent: March 7, 2017Assignee: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Sanjeev Dwarakanath, Jitendra Ramkrishna Kulkarni, Rishi Agarwal
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Publication number: 20170017496Abstract: Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with USB 3.0. The host device comprises a reduced functionality USB host controller configured to perform a set of one or more preprogrammed functions from the USB 3.0 specification, and a universal asynchronous receiver and transmitter (UART) configured to sample USB response data received from the peripheral device over the bus.Type: ApplicationFiled: September 27, 2016Publication date: January 19, 2017Inventors: Pradeep Kumar Bajpai, Robert G. Rundell
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Publication number: 20160028252Abstract: Techniques for controlling the charging of portable devices are described herein. In an example embodiment, an apparatus comprises a controller coupled to a Universal Serial Bus (USB) port that is configured as a dedicated charging port (DCP). The controller is configured to detect whether a battery-charging (BC) compliant device or a BC non-compliant device is attached to the USB port. When a BC compliant device is detected, the controller controls the charging of the BC compliant device (e.g., by providing a maximum of 1.5 A of charging current). When a BC non-compliant device is detected, the controller controls the charging of the BC non-compliant device by providing a higher (e.g., up to 2.4 A) charging current.Type: ApplicationFiled: June 25, 2015Publication date: January 28, 2016Inventors: Pradeep Kumar Bajpai, Sanjeev Dwarakanath, Jitendra Ramkrishna Kulkarni, Rishi Agarwal