Abstract: The present disclosure relates to a change engine system (104) and a method thereof for automatic interference mitigation in a network. The change engine system (104) receives a plurality of change requests. The system (106) determines interference network cell data from the received plurality of change requests. Further, the system (106) indexes and segments the determined interference network cell data across a plurality of states and a plurality of network elements and determines a change parameter of a plurality of change parameters. Also, the system (106) determines a command of a plurality of commands based on the determined change parameter and applies the command on the plurality of network elements to automatically mitigate the interference in the network.

Abstract: The present disclosure provides system (102) and method (300) for enabling speed test of internet connection using a mobile application. The mobile application selects an appropriate server and initiates the data transfer by sending and receiving packets of data to and from the server. The data size and duration of the test can vary, but larger sample sizes generally provide more accurate results therefore multiple threads with increasing buffer size are used during the test time. The system measures the time it takes for the data transfer to complete in both the upload and download directions. The timing is crucial for determining the speeds. A speed test empowers users with the ability to measure, evaluate, and understand the performance of the internet connection. Thus, enabling the users to make informed decisions and ensure they receive reliable and satisfactory internet service.

Abstract: An ATM switch having a plurality of input-ports and a plurality of output ports allowing a plurality of priority levels, which is highly modular allowing expansion of the number of cell buffers in a shared buffer pool, thus efficiently handling bursty traffic of one-to-one and one-to-many destination ports, using the bit slicing concept to reduce the operating speed of the switch, and decrease the cell buffer size requirement per slice along with reducing the number of shared queue memories per slice, aiding cost effective and efficient, very large scale integration (VLSI) implementation. It also allows configurability of input link speeds, taking care of the order of cell delivery to the output ports. The switch on receiving the input cell, searches for a free buffer in the shared pool, then routes the cell into this buffer and indexes the pointer into an output queue called the queue management module which uses a shared pool of queue memories.