Abstract: User Equipment (UE) band capabilities are received from a UE. A set of frequency band combinations are determined for the UE based on the UE band capabilities. Each frequency band combination of the set of frequency band combinations includes a group of frequency bands, and a frequency band combination priority value. Further, one or more frequency band combinations are identified from the set of frequency band combinations based on a current frequency band of the UE and the frequency band combination priority value. The UE is configured to perform frequency measurements for a plurality of frequency bands based on the one or more identified frequency band combinations. The UE is dynamically facilitated to latch to at least one frequency band based on the frequency measurements of the plurality of frequency bands.

Abstract: A network system includes a non-transitory computer readable medium configured to store instructions thereon; and a processor. The processor is configured to execute the instructions for providing a first information element in a protocol, wherein the first information element is usable to configure parameters associated with convergence of packet data; providing a second information element within the first information element, wherein the second information element is usable for a first range of logical channels; and providing a third information element within the first information element, wherein the third information element is usable for a second range of logical channels outside of the first range of logical channels.

Abstract: A method for implementing dynamic content handling of inter layer messages in a pod based cloud native environment, the method includes: receiving, by a virtual centralized unit (vCU), at least one Master Information Block (MIB) parameter configured by a virtual element management system (vEMS); preparing, by the vCU, a MIB encoded buffer may include a Dummy System Frame Number (D-SFN); sending, by the vCU, once at the time of startup initiation, the MIB encoded buffer with the D-SFN to a virtual distributed unit (vDU) via a Midhaul between the vCU and the vDU; receiving, by the vDU, the MIB encoded buffer with the D-SFN via the Midhaul; for each received MIB encoded buffer, by the vDU, calculating a new SFN from an utility function; updating the MIB encoded buffer; and sending the updated MIB encoded buffer with the new SFN from the utility function to a user entity (UE).

Abstract: An Open Radio Access Network (O-RAN) communication system includes a GNB Central Unit Control Plane (GNB-CUCP) to establish a connection with a Near-RT RIC via an E2 interface; a User Equipment (UE); a plurality of cells in a Tracking Area (TA) of the GNB-CUCP; and an O-RAN Near-Real Time (Near-RT) RAN Intelligent Controller (RIC) to host an xApp and initiate a subscription procedure with the UE. The GNB-CUCP sends cell location information of the UE to the Near-RT RIC upon a UE context release procedure, the Near-RT RIC creates and maintains a record of the cell location information received from the GNB-CUCP via the xApp, and the GNB-CUCP pages the UE in a subset of cells from the plurality of cells in the TA, the subset of cells corresponding to the record of cell location information created and maintained by via the xApp.

Abstract: Computer-implemented methods, apparatuses, and non-transitory storage media for determining peak connections in a distributed environment are provided. In some implementations, determining peak connections in a distributed environment can include receiving, according to a predetermined time schedule, data indicating a number of user equipments (UEs) connected to and a number of UEs disconnected from each of a plurality of scheduling units of a radio access network (RAN) during each of a plurality of time windows in a first period of time, determining, based on the received data, a maximum number of UEs connected to the scheduling units at a time in the first period of time, and transmitting the determined maximum number of UEs to a network manager of the RAN.

Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: Provided is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of integrated circuit device. The method can further include determining target gates referred to as trace signals within integrated circuit device. The method can further include creating hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving the scalability of connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: A computing system determines a first set of registers having constant next-state functions in the netlist. The computing system identifies an observable gate in fan-out of a register in the first set, wherein an observable gate is a gate that is critical to a verification or synthesis context. The computing system identifies a second set of reducible registers in the fan-in of the observable gate. The computing system modifies at least one of an initial value and a next-state function of at least one reducible register of the second set to reflect an observable value of the at least one reducible register observed at the observable gate. The computing system simplifies one or more logic gates implementing the observable gate and the fan-in of the observable gate by eliminating a reference to a constant next-state function register in the first set of registers.

Abstract: A computing system determines a first set of registers having constant next-state functions in the netlist. The computing system identifies an observable gate in fan-out of a register in the first set, wherein an observable gate is a gate that is critical to a verification or synthesis context. The computing system identifies a second set of reducible registers in the fan-in of the observable gate. The computing system modifies at least one of an initial value and a next-state function of at least one reducible register of the second set to reflect an observable value of the at least one reducible register observed at the observable gate. The computing system simplifies one or more logic gates implementing the observable gate and the fan-in of the observable gate by eliminating a reference to a constant next-state function register in the first set of registers.

Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: A logic verification program, method and system provide an efficient behavior when verifying large logic designs. The logic is partitioned by cut-nodes that dominate two or more RANDOMS and a check is performed for a given cut-node to determine whether any of the dominated RANDOMS can be merged to a constant by performing satisfiability checks with each RANDOM merged to a constant, to determine whether a range of output values for the given cut-node has been reduced by merging the RANDOM. If the range is not reduced, the RANDOM can be added to the set of merge-able RANDOMS along with the corresponding constant value. If the range has been reduced, the opposite constant value is tried for a node and if the range is reduced for both constants, then the cut-node is abandoned for merging that dominated RANDOM and the next dominated RANDOM is tried.

Abstract: A logic verification program, method and system provide an efficient behavior when verifying large logic designs. The logic is partitioned by cut-nodes that dominate two or more RANDOMS and a check is performed for a given cut-node to determine whether any of the dominated RANDOMS can be merged to a constant by performing satisfiability checks with each RANDOM merged to a constant, to determine whether a range of output values for the given cut-node has been reduced by merging the RANDOM. If the range is not reduced, the RANDOM can be added to the set of merge-able RANDOMS along with the corresponding constant value. If the range has been reduced, the opposite constant value is tried for a node and if the range is reduced for both constants, then the cut-node is abandoned for merging that dominated RANDOM and the next dominated RANDOM is tried.

Abstract: A computer implemented method for increasing scalability in bounded liveness verification includes receiving, by one or more processors, a counterexample trace showing a bounded liveness failure and a set of parameters associated with the counterexample trace, partitioning the counterexample trace into segments representing bound increments contributing to the bounded liveness failure, selecting, by one or more processors, a time interval during which to repeat input values, wherein the selected time interval correlates to one or more segments, evaluating, by one or more processors, the received counterexample after repeating the selected time interval, determining, by one or more processors, whether the evaluation indicates that the counterexample falsifies a deeper bound with respect to a bound or an unbounded liveness counterexample, and, responsive to determining the evaluation indicates that the counterexample falsifies a deeper bound, providing, by one or more processors, counterexample falsification re

Abstract: Provided is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of integrated circuit device. The method can further include determining target gates referred to as trace signals within integrated circuit device. The method can further include creating hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving the scalability of connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.

Abstract: A computer implemented method for increasing scalability in bounded liveness verification includes receiving, by one or more processors, a counterexample trace showing a bounded liveness failure and a set of parameters associated with the counterexample trace, partitioning the counterexample trace into segments representing bound increments contributing to the bounded liveness failure, selecting, by one or more processors, a time interval during which to repeat input values, wherein the selected time interval correlates to one or more segments, evaluating, by one or more processors, the received counterexample after repeating the selected time interval, determining, by one or more processors, whether the evaluation indicates that the counterexample falsifies a deeper bound with respect to a bound or an unbounded liveness counterexample, and, responsive to determining the evaluation indicates that the counterexample falsifies a deeper bound, providing, by one or more processors, counterexample falsification re

Abstract: A method includes configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, simulating N clock cycles in the circuit to provide performance results for one or more registers in the circuit, wherein N is a selected number of staging levels, selecting one of the one or more registers, comparing the performance results for the selected register to performance results for each of the remaining registers to provide one or more equivalent delay candidate registers, and verifying each of the one or more equivalent delay candidate registers to provide one or more confirmed equivalent delay registers. A corresponding computer program product and computer system are also disclosed.

Abstract: A method includes configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, simulating N clock cycles in the circuit to provide performance results for one or more registers in the circuit, wherein N is a selected number of staging levels, selecting one of the one or more registers, comparing the performance results for the selected register to performance results for each of the remaining registers to provide one or more equivalent delay candidate registers, and verifying each of the one or more equivalent delay candidate registers to provide one or more confirmed equivalent delay registers. A corresponding computer program product and computer system are also disclosed.

Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.

Abstract: A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.