Abstract: In an example implementation consistent with the features disclosed herein, high availability of a stateful application is achieved by orchestrating multiple computing clusters. A stateful application is deployed at a first application operator and a second application operator of a first computing cluster and a second computing cluster, respectively. The first application operator includes a first control loop that changes the first computing cluster based on first resources of the first computing cluster. The second application operator includes a second control loop that changes the second computing cluster based on second resources of the second computing cluster. Synchronization of the first resources with the second resources is configured, such as via an object storage service. The first application operator and the second application operator are scaled to, respectively, nonzero and zero. A load balancer is configured to route requests to the first computing cluster.

Abstract: SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.