Patents by Inventor Pradeep Nagarajan

Pradeep Nagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10938678
    Abstract: A device may obtain ticket data relating to a set of tickets, and process the ticket data to generate a ticket analysis model that is a clustering based natural language analysis model of natural language text associated with tickets of the set of tickets. The device may classify the set of tickets using the ticket analysis model, may determine an automation plan for at least one class of ticket determined based on classifying the set of tickets, and may implement the automation plan to configure an automatic ticket resolution or ticket generation mitigation procedure for the at least one class of ticket. The device may receive a ticket after configuring the automatic ticket resolution or ticket generation mitigation procedure, may classify, using the ticket analysis model, the ticket into the at least one class of ticket, and may automatically implement a response action for the ticket based on classifying the ticket and using the automatic ticket resolution or ticket generation mitigation procedure.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: March 2, 2021
    Assignee: Accenture Global Solutions Limited
    Inventors: Bhaskar Ghosh, Mohan Sekhar, Rajendra T. Prasad, Luke Higgins, Koushik Vijayaraghavan, Rajesh Nagarajan, Purnima Jagannathan, Niyaz Shaffi, Balaji Venkateswaran, Syed Mohammed Yusuf, Koustuv Jana, Pradeep Senapati
  • Patent number: 10845335
    Abstract: An electrochemical tongue can be used for detection of metal ions. The reference electrode of the electrochemical tongue can be coated with a polymer. More than one reference electrode can be used, and the electrochemical tongue can be inserted into a cone penetrometer for portable, in situ analysis.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: November 24, 2020
    Assignee: University of Massachusetts
    Inventors: Pradeep Kurup, Ramaswamy Nagarajan, Timothy Ponrathnam, Weeradech Kiratitanavit
  • Patent number: 10831448
    Abstract: A device may obtain process data relating to a set of processes. The device may process the process data to generate a process analysis model. The device may classify, using the process analysis model, a particular process into a particular class of a set of classes of the process analysis model. The device may automatically assess the particular process based on the particular class, wherein a set of assessment parameters for assessing the particular process is selected based on the particular class, and wherein an assessment score is assigned to the particular process based on values for the set of assessment parameters. The device may determine, based on the assessment score and the particular class, an automation recommendation for the particular process. The device may automatically complete the particular process using a particular tool based on determining the automation recommendation.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: November 10, 2020
    Assignee: Accenture Global Solutions Limited
    Inventors: Rajendra T. Prasad, Bhaskar Ghosh, Mohan Sekhar, Priya Athreyee, Koustuv Jana, Koushik Vijayaraghavan, Amaresh Swain, Pradeep Senapati, Kamakshi Girish, Lakshmi Narasimhan, Somen Roy, Rajesh Nagarajan, Senthil Jeyachandran, Arulmozhi Dharmar
  • Publication number: 20200073639
    Abstract: A device may obtain process data relating to a set of processes. The device may process the process data to generate a process analysis model. The device may classify, using the process analysis model, a particular process into a particular class of a set of classes of the process analysis model. The device may automatically assess the particular process based on the particular class, wherein a set of assessment parameters for assessing the particular process is selected based on the particular class, and wherein an assessment score is assigned to the particular process based on values for the set of assessment parameters. The device may determine, based on the assessment score and the particular class, an automation recommendation for the particular process. The device may automatically complete the particular process using a particular tool based on determining the automation recommendation.
    Type: Application
    Filed: April 5, 2019
    Publication date: March 5, 2020
    Inventors: Rajendra T. PRASAD, Bhaskar GHOSH, Mohan SEKHAR, Priya ATHREYEE, Koustuv JANA, Koushik VIJAYARAGHAVAN, Amaresh SWAIN, Pradeep SENAPATI, Kamakshi GIRISH, Lakshmi NARASIMHAN, Somen ROY, Rajesh NAGARAJAN, Senthil JEYACHANDRAN, Arulmozhi DHARMAR
  • Publication number: 20200065151
    Abstract: A device may obtain ticket data relating to a set of tickets, and process the ticket data to generate a ticket analysis model that is a clustering based natural language analysis model of natural language text associated with tickets of the set of tickets. The device may classify the set of tickets using the ticket analysis model, may determine an automation plan for at least one class of ticket determined based on classifying the set of tickets, and may implement the automation plan to configure an automatic ticket resolution or ticket generation mitigation procedure for the at least one class of ticket. The device may receive a ticket after configuring the automatic ticket resolution or ticket generation mitigation procedure, may classify, using the ticket analysis model, the ticket into the at least one class of ticket, and may automatically implement a response action for the ticket based on classifying the ticket and using the automatic ticket resolution or ticket generation mitigation procedure.
    Type: Application
    Filed: March 20, 2019
    Publication date: February 27, 2020
    Inventors: Bhaskar GHOSH, Mohan SEKHAR, Rajendra T. PRASAD, Luke HIGGINS, Koushik VIJAYARAGHAVAN, Rajesh NAGARAJAN, Purnima JAGANNATHAN, Niyaz SHAFFI, Balaji VENKATESWARAN, Syed MOHAMMED YUSUF, Koustuv JANA, Pradeep SENAPATI
  • Publication number: 20180278406
    Abstract: Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 27, 2018
    Inventors: Chaitanya Palusa, Dawei Huang, Jiangyuan Li, Pradeep Nagarajan
  • Patent number: 10084591
    Abstract: Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: September 25, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Chaitanya Palusa, Dawei Huang, Jiangyuan Li, Pradeep Nagarajan
  • Patent number: 9711189
    Abstract: A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: July 18, 2017
    Assignee: Altera Corporation
    Inventors: Bonnie I. Wang, Chiakang Sung, Xiaobao Wang, Yan Chong, Joseph Huang, Khai Nguyen, Pradeep Nagarajan
  • Patent number: 9158873
    Abstract: Systems and methods are disclosed for calibrating a Data Strobe (DQS) enable/disable signal and for tracking the timing of the DQS enable/disable signal with respect to changes in voltage and temperature (VT) in order to improve the timing margin of the DQS enable/disable signal in programmable devices using Double Data Rate (DDR) memory. In an exemplary embodiment, the system includes a gating circuit, a sampling circuit, and a delay chain tracking circuit. The gating circuit receives a DQS enable signal and a input DQS signal, calibrates the DQS enable signal based on an amount of delay, and outputs the calibrated DQS signal. The sampling circuit provides the amount of delay to the gating circuit based on a sampling clock. The delay chain tracking circuit maintains the timing of the calibrated DQS enable signal over a plurality of clock cycles based on the sampling clock and a leveling clock.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: October 13, 2015
    Assignee: Altera Corporation
    Inventors: Yan Chong, Joseph Huang, Sean Shau-Tu Lu, Pradeep Nagarajan, Chiakang Sung
  • Patent number: 9059716
    Abstract: A circuit-includes a delay locked loop (DLL), a calibration circuit and an output delay chain controlled by the calibration circuit. The DLL comprises a plurality of series-coupled first delay elements, each of which has substantially the same first delay. The calibration circuit comprises a plurality of series-coupled second delay elements, each of which has substantially the same second delay that is less than the first delay, a first delay element, and a circuit for determining the minimum number of second delay elements that are needed to produce the first delay. The output delay chain comprises a plurality of series-coupled second delay elements, an input for receiving the input signal, and a circuit for selectively tapping the output delay chain at a plurality of taps in the output delay chain so as to produce in the input signal different delays of integral multiples of the second delay.
    Type: Grant
    Filed: March 15, 2014
    Date of Patent: June 16, 2015
    Assignee: Altera Corporation
    Inventors: Pradeep Nagarajan, Yan Chong, Sean Shau-Tu Lu, Chiakang Song, Joseph Huang
  • Patent number: 8847626
    Abstract: A circuit includes first and second bidirectional clock networks and first and second clock signal generation circuits. A first multiplexer circuit is configurable to provide a first clock signal from a first pin to the first bidirectional clock network. A second multiplexer circuit is configurable to provide the first clock signal from the first bidirectional clock network to the second bidirectional clock network. Third multiplexer circuits are configurable to provide the first clock signal from the second bidirectional clock network to the first and the second clock signal generation circuits.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Altera Corporation
    Inventors: Yan Chong, Warren Nordyke, Pradeep Nagarajan, James Kimble Lin, Weiqi Ding
  • Patent number: 8787097
    Abstract: Systems and methods are disclosed for calibrating a Data Strobe (DQS) enable/disable signal and for tracking the timing of the DQS enable/disable signal with respect to changes in voltage and temperature (VT) in order to improve the timing margin of the DQS enable/disable signal in programmable devices using Double Data Rate (DDR) memory. In an exemplary embodiment, the system includes a gating circuit, a sampling circuit, and a delay chain tracking circuit. The gating circuit receives a DQS enable signal and a input DQS signal, calibrates the DQS enable signal based on an amount of delay, and outputs the calibrated DQS signal. The sampling circuit provides the amount of delay to the gating circuit based on a sampling clock. The delay chain tracking circuit maintains the timing of the calibrated DQS enable signal over a plurality of clock cycles based on the sampling clock and a leveling clock.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: July 22, 2014
    Assignee: Altera Corporation
    Inventors: Yan Chong, Joseph Huang, Sean Shau-Tu Lu, Pradeep Nagarajan, Chiakang Sung
  • Patent number: 8680905
    Abstract: A circuit includes a delay locked loop (DLL), a calibration circuit and an output delay chain controlled by the calibration circuit. The DLL comprises a plurality of series-coupled first delay elements each of which has substantially the same first delay. The calibration circuit comprises a plurality of series-coupled second delay elements, each of which has substantially the same second delay that is less than the first delay, a first delay element, and a circuit for determining the minimum number of second delay elements that are needed to produce the first delay. The output delay chain comprises a plurality of series-coupled second delay elements, an input for receiving the input signal, and a circuit for selectively tapping the output delay chain at a plurality of taps in the output delay chain so as to produce in the input signal different delays of integral multiples of the second delay.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: March 25, 2014
    Assignee: Altera Corporation
    Inventors: Pradeep Nagarajan, Yan Chong, Sean Shau-Tu Lu, Chiakang Sung, Joseph Huang
  • Patent number: 8624647
    Abstract: Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: January 7, 2014
    Assignee: Altera Corporation
    Inventors: Yan Chong, Joseph Huang, Pradeep Nagarajan, Chiakang Sung
  • Patent number: 8565034
    Abstract: Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data and data strobe signals from system memory during read operations. The memory interface circuitry may include de-skew circuitry and dynamic variation compensation circuitry. The de-skew circuitry may be configured during calibration procedures to reduce skew between the data and data strobe signals. The dynamic variation compensation circuitry may be used in real time to compensate for variations in operating conditions.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 22, 2013
    Assignee: Altera Corporation
    Inventors: Sean Shau-Tu Lu, Joseph Huang, Yan Chong, Pradeep Nagarajan, Chiakang Sung
  • Patent number: 8237475
    Abstract: A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: August 7, 2012
    Assignee: Altera Corporation
    Inventors: Pradeep Nagarajan, Sean Shau-Tu Lu, Chiakang Sung, Joseph Huang, Yan Chong
  • Patent number: 8159277
    Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: April 17, 2012
    Assignee: Altera Corporation
    Inventors: Pradeep Nagarajan, Yan Chong, Chiakang Sung, Joseph Huang
  • Patent number: 8130016
    Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: March 6, 2012
    Assignee: Altera Corporation
    Inventors: Pradeep Nagarajan, Yan Chong, Chiakang Sung, Joseph Huang
  • Publication number: 20110175657
    Abstract: Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.
    Type: Application
    Filed: January 19, 2010
    Publication date: July 21, 2011
    Inventors: Yan Chong, Joseph Huang, Pradeep Nagarajan, Chiakang Sung
  • Publication number: 20110074477
    Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.
    Type: Application
    Filed: December 18, 2009
    Publication date: March 31, 2011
    Applicant: ALTERA CORPORATION
    Inventors: Pradeep Nagarajan, Yan Chong, Chiakang Sung, Joseph Huang