Patents by Inventor Pradeep NIROULA

Pradeep NIROULA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260099743
    Abstract: Systems and methods for optimizing parameterized quantum circuits for combinatorial optimization and machine learning tasks using coordinate-descent are disclosed. A classical computer program constructs a plurality of parameterized quantum circuits with quantum circuit for an objective function and selects Pauli operators associated with decision variables. The classical computer program sends the parameterized quantum circuits and Pauli operators to a quantum computer, which executes the circuits and measures the decision variables. The classical computer program receives the measurements, calculates an objective value, and determines if a stopping criterion is met. If the stopping criterion is not met, the classical computer program selects a parameter, instructs the quantum computer to execute the circuits with the selected parameter, and computes an optimized value. The process repeats until the stopping criterion is met, and the objective value is outputted.
    Type: Application
    Filed: October 2, 2024
    Publication date: April 9, 2026
    Inventors: Rudy Raymond Harry PUTRA, Pradeep NIROULA, Alexander BUTS, Marco PISTOIA
  • Patent number: 12524555
    Abstract: A method may include: generating, by a plurality of auditor computer programs and a data curator computer program, a first random string using a first distributed randomness protocol; sending the first random string to a quantum party computer program; executing, by the quantum party computer program, a certified randomness protocol with a quantum randomness source using the first random string; receiving, from the quantum randomness source, a first quantum randomness; generating, by the auditor computer programs and the data curator computer program, a second random string using a second distributed randomness protocol; extracting, by the data curator computer program and using a randomness extractor, a second quantum randomness from the first quantum randomness using the second random string, wherein the second quantum randomness comprises a near-uniformly random string; and executing, by the data curator computer program, a differential privacy protocol using the second quantum randomness as additive noise
    Type: Grant
    Filed: May 31, 2024
    Date of Patent: January 13, 2026
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Andrew Lang, Marco Pistoia, Omar Amer, Shouvanik Chakrabarti, Niraj Kumar, Pradeep Niroula, Ruslan Shaydulin
  • Publication number: 20250370718
    Abstract: A method may include: selecting, by a plurality of classical parties, each of the classical parties using a classical party computer program, a distributed randomness protocol; generating, by the plurality of classical parties, a random string using the selected distributed randomness protocol; providing, by one of the classical parties, the random string to a quantum party, wherein the quantum party executes a quantum party computer program in communication with a quantum randomness source; executing, by the quantum party, a certified randomness protocol with the quantum randomness source using the random string as an input; receiving, by the quantum party, quantum randomness comprising a sequence of random bits from the quantum randomness source; and verifying, by the classical parties, that the random string was randomly selected, and that the quantum randomness is a valid output of the certified randomness protocol using the random string as input.
    Type: Application
    Filed: May 31, 2024
    Publication date: December 4, 2025
    Inventors: Omar AMER, Shouvanik CHAKRABARTI, Niraj KUMAR, Pradeep NIROULA, Ruslan SHAYDULIN, Marco PISTOIA, Andrew LANG
  • Publication number: 20250371172
    Abstract: A method may include: generating, by a plurality of auditor computer programs and a data curator computer program, a first random string using a first distributed randomness protocol; sending the first random string to a quantum party computer program; executing, by the quantum party computer program, a certified randomness protocol with a quantum randomness source using the first random string; receiving, from the quantum randomness source, a first quantum randomness; generating, by the auditor computer programs and the data curator computer program, a second random string using a second distributed randomness protocol; extracting, by the data curator computer program and using a randomness extractor, a second quantum randomness from the first quantum randomness using the second random string, wherein the second quantum randomness comprises a near-uniformly random string; and executing, by the data curator computer program, a differential privacy protocol using the second quantum randomness as additive noise
    Type: Application
    Filed: May 31, 2024
    Publication date: December 4, 2025
    Inventors: Andrew LANG, Marco PISTOIA, Omar AMER, Shouvanik CHAKRABARTI, Niraj KUMAR, Pradeep NIROULA, Ruslan SHAYDULIN
  • Patent number: 12488276
    Abstract: A method of determining a pattern in a sequence of bits using a quantum computing system includes setting a first register of a quantum processor in a superposition of a plurality of string index states, encoding a bit string in a second register of the quantum processor, encoding a bit pattern in a third register of the quantum processor, circularly shifting qubits of the second register conditioned on the first register, amplifying an amplitude of a state combined with the first register in which the circularly shifted qubits of the second register matches qubits of the third register, measuring an amplitude of the first register and determining a string index state of the plurality of string index states associated with the amplified state, and outputting, by use of a classical computer, a string index associated with the first register in the measured state.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: December 2, 2025
    Assignees: IONQ, INC., UNIVERSITY OF MARYLAND
    Inventors: Pradeep Niroula, Yunseong Nam
  • Patent number: 12481719
    Abstract: A method for implementing all-to-all connectivity in gate-based quantum computers may include a classical computer program: receiving an optimization problem; constructing a problem Hamiltonian by assigning a qubit to each interactions between pairs of variables; associating each of the assigned qubits to a physical qubit in a physical qubit grid; assigning readout physical qubits in the physical qubit grid to neighbors of the associated physical qubits; instructing the quantum computer to apply a driving Hamiltonian and the problem Hamiltonian to the physical qubit grid; instructing the quantum computer to apply CNOT gates between associated physical qubits on edges of each triangle and square in the physical qubit grid and the readout physical qubits in centers of the triangles and squares; instructing the quantum computer to measure the readout physical qubits; and determining that the measurements of all readout physical indicates that parities between the physical qubits are enforced.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: November 25, 2025
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Pradeep Niroula, Marco Pistoia
  • Publication number: 20250315212
    Abstract: A method may include: (1) querying, by a randomness computer program executed by a randomness electronic device, a quantum randomness source for a plurality of sequences of random bits; (2) receiving, by the randomness computer program, the plurality of sequences of random bits; (3) saving, by the randomness computer program, the plurality of sequences of random bits in a randomness pool; (4) receiving, by the randomness computer program, a request for randomness from a client randomness computer program executed by a client electronic device; (5) drawing, by the randomness computer program, a subset of the plurality of sequences of random bits from the randomness pool; (6) marking, by the randomness computer program, the subset of the plurality of sequences of random bits as used; and (7) communicating, by the randomness computer program, the subset of the plurality of sequences of random bits to the client randomness computer program.
    Type: Application
    Filed: April 3, 2024
    Publication date: October 9, 2025
    Inventors: Pradeep NIROULA, Ruslan SHAYDULIN, Shouvanik CHAKRABARTI, Omar AMER, Marco PISTOIA, Andrew LANG
  • Publication number: 20250315704
    Abstract: A method may include: (1) generating, by a classical computer program executed by a client electronic device, a pseudorandom graph having a depth, a number of nodes based on a number of qubits in a quantum computer, and edges between the nodes; (2) creating, by the classical computer program, a coloring of the graph such that no two edges that share a node have the same color; (3) creating, by the classical computer program, a graph coloring layer for each color that includes edges with that color; (4) generating, by the classical computer, a quantum circuit from the graph coloring layers; (5) estimating, by the classical computer program, a cost of validating the quantum circuit; (6) determining, by the classical computer program, that the cost is acceptable; and (7) saving, by the classical computer program, the quantum circuit in response to the cost being acceptable.
    Type: Application
    Filed: April 3, 2024
    Publication date: October 9, 2025
    Inventors: Ruslan SHAYDULIN, Pradeep NIROULA, Marco PISTOIA, Andrew LANG, Minzhao LIU
  • Patent number: 12430484
    Abstract: A method of performing a computational process includes transforming, a first register of a quantum processor to a charge encoded state in which charges of interacting particles to be simulated are encoded, transforming a second register of the quantum processor to a position encoded state in which positions of the interacting particles are encoded, performing a first phase shift operation, including shifting a phase of the first and second registers by kinetic energies of the interacting particles, performing a second phase shift operation, including shifting the phase of the first and second registers by pair-wise Coulomb potential energies of the interacting particles, measuring the phase of the first and second registers, transmitting the measured phase of the first and second registers to a classical computer, and the measured phase including a sum of the kinetic energies and the pair-wise Coulomb potential energies of the interacting particles.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: September 30, 2025
    Assignees: UNIVERSITY OF MARYLAND, COLLEGE PARK, IONQ, INC.
    Inventors: Pradeep Niroula, Wengang Zhang, Yunseong Nam
  • Patent number: 12424302
    Abstract: A method of performing computation using a hybrid quantum-classical computing system comprising a classical computer and a quantum processor includes computing, by use of a classical computer, short-range inter-particle interaction energies and self-energies of a group of interacting particles, transforming the quantum processor from an initial state to a charge-position encoded state, applying Quantum Fourier transformation to the quantum processor, measuring an estimated amplitude of the Fourier transformed superposition state on the quantum processor, computing long-range inter-particle interaction energies based on the measured estimated amplitude of the Fourier transformed superposition state, and computing and outputting a sum of the short-range inter-particle interaction energies, the self-energies of the system, and the long-range inter-particle interaction energies as a total inter-particle interaction energies of the system.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: September 23, 2025
    Assignee: IONQ, INC.
    Inventors: Pradeep Niroula, Wengang Zhang, Yunseong Nam
  • Publication number: 20250245557
    Abstract: Systems and methods for approximation of Shapley values in memory-constrained environments are disclosed. According to an embodiment, a method may include: (1) receiving, by a training computer program executed on a training electronic device, a training dataset; (2) training, by the training computer program, a machine learning model on the training dataset; (3) deploying, by the training computer program, the machine learning model to a deployment electronic device; (4) receiving, by the deployment electronic device, an incoming data query; (5) generating, using the machine learning model, a prediction for the incoming data query; and (6) estimating, by a model explanation computer program, a Shapley value for the prediction.
    Type: Application
    Filed: January 30, 2024
    Publication date: July 31, 2025
    Inventors: Pradeep NIROULA, Niraj KUMAR, Shouvanik CHAKRABARTI, Romina YALOVETZKY, Marco PISTOIA
  • Publication number: 20250231741
    Abstract: In some aspects, the techniques described herein relate to a method including: executing a data structure initialization process, wherein the data structure initialization process takes a real-valued array as input and creates a bag data structure for each vector in a set of vectors, and wherein the bag data structure for each vector in a set of vectors includes an index array and a probability array; providing, as input to a primary maximum inner product search process, the set of vectors, a stream of vectors, and the bag data structure for each of the vectors in the set; and determining, by a secondary maximum inner product search process for each vector in the stream of vectors, an index of the set of vectors such that the index has a maximum inner product with the vector from the stream of vectors.
    Type: Application
    Filed: January 12, 2024
    Publication date: July 17, 2025
    Inventors: Arthur G RATTEW, Shouvanik CHAKRABARTI, Yue SUN, Pradeep NIROULA, Marco PISTOIA
  • Patent number: 12353957
    Abstract: A method of performing computation using an ion trap quantum computing system including a classical computer, a system controller, and a quantum processor includes computing, by the classical computer, a circuit that implements a selected set of gate operations, using one or more efficient arbitrary simultaneous entangling (EASE) gates, implementing, by the system controller, the computed circuit on the quantum processor, measuring, by the system controller, population of qubit states in the quantum processor, and outputting, by the classical computer, the measured population of qubit states in the quantum processor.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: July 8, 2025
    Assignee: IONQ, INC.
    Inventors: Nikodem Grzesiak, Andrii Maksymov, Pradeep Niroula, Yunseong Nam
  • Patent number: 12229603
    Abstract: A method of performing a quantum computation process includes mapping logical qubits to physical qubits of a quantum processor so that quantum circuits are executable using the physical qubits of the quantum processor and a total infidelity of the plurality of quantum circuits is minimized, wherein each of the physical qubits comprise a trapped ion, and each of the plurality of quantum circuits comprises single-qubit gates and two-qubit gates within the plurality of the logical qubits, calibrating two-qubit gates within a first plurality of pairs of physical qubits, such that infidelity of the two-qubit gates within the first plurality of pairs of physical qubit is lowered, executing the plurality of quantum circuits on the quantum processor, by applying laser pulses that each cause a single-qubit gate operation and a two-qubit gate operation in each of the plurality of quantum circuits on the plurality of physical qubits, measuring population of qubit states of the physical qubits in the quantum processor, a
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 18, 2025
    Assignees: IONQ, INC., UNIVERSITY OF MARYLAND
    Inventors: Andrii Maksymov, Pradeep Niroula, Yunseong Nam
  • Patent number: 12093128
    Abstract: Systems and methods for efficient error mitigation in quantum circuit execution using parity checks and classical feedback are disclosed.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: September 17, 2024
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Pradeep Niroula, Ruslan Shaydulin, Marco Pistoia
  • Publication number: 20240185109
    Abstract: A process for measuring multiple functions with a quantum sensor network includes: providing a plurality of quantum sensors, each of which is configured for measuring a different analytic function of a set of unknown parameters; preparing the plurality of quantum sensors in a known state; exposing the plurality of quantum sensors to the set of unknown parameters; measuring the plurality of quantum sensors; and calculating the multiple analytic functions of the set of unknown parameters from the measurements of the plurality of quantum sensors
    Type: Application
    Filed: April 18, 2023
    Publication date: June 6, 2024
    Inventors: Alexey Vyacheslavovich Gorshkov, Jacob Bringewatt, Igor Boettcher, Pradeep Niroula, Przemyslaw Bienias
  • Publication number: 20240176694
    Abstract: Systems and methods for efficient error mitigation in quantum circuit execution using parity checks and classical feedback are disclosed.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Pradeep NIROULA, Ruslan SHAYDULIN, Marco PISTOIA
  • Publication number: 20240013078
    Abstract: A method of determining a pattern in a sequence of bits using a quantum computing system includes setting a first register of a quantum processor in a superposition of a plurality of string index states, encoding a bit string in a second register of the quantum processor, encoding a bit pattern in a third register of the quantum processor, circularly shifting qubits of the second register conditioned on the first register, amplifying an amplitude of a state combined with the first register in which the circularly shifted qubits of the second register matches qubits of the third register, measuring an amplitude of the first register and determining a string index state of the plurality of string index states associated with the amplified state, and outputting, by use of a classical computer, a string index associated with the first register in the measured state.
    Type: Application
    Filed: September 18, 2023
    Publication date: January 11, 2024
    Inventors: Pradeep NIROULA, Yunseong NAM
  • Patent number: 11823010
    Abstract: A method of determining a pattern in a sequence of bits using a quantum computing system includes setting a first register of a quantum processor in a superposition of a plurality of string index states, encoding a bit string in a second register of the quantum processor, encoding a bit pattern in a third register of the quantum processor, circularly shifting qubits of the second register conditioned on the first register, amplifying an amplitude of a state combined with the first register in which the circularly shifted qubits of the second register matches qubits of the third register, measuring an amplitude of the first register and determining a string index state of the plurality of string index states associated with the amplified state, and outputting, by use of a classical computer, a string index associated with the first register in the measured state.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 21, 2023
    Assignees: IONQ, INC., UNIVERSITY OF MARYLAND
    Inventors: Pradeep Niroula, Yunseong Nam
  • Publication number: 20230259804
    Abstract: A method of performing computation using an ion trap quantum computing system including a classical computer, a system controller, and a quantum processor includes computing, by the classical computer, a circuit that implements a selected set of gate operations, using one or more efficient arbitrary simultaneous entangling (EASE) gates, implementing, by the system controller, the computed circuit on the quantum processor, measuring, by the system controller, population of qubit states in the quantum processor, and outputting, by the classical computer, the measured population of qubit states in the quantum processor.
    Type: Application
    Filed: July 11, 2022
    Publication date: August 17, 2023
    Inventors: NIKODEM GRZESIAK, Andrii Maksymov, Pradeep Niroula, Yunseong Nam