Patents by Inventor Pradeep Patil
Pradeep Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240080033Abstract: Continuous-time (CT) analog-to-digital converters (ADCs) implementing digital correction of digital-to-analog converter (DAC) errors are disclosed. In a CT pipeline stage of a CT ADC, a CT analog input signal is sent to two different paths. A first path (a “feedforward” path) includes a cascade of a sub-ADC and a sub-DAC. A second path (a “forward” path) includes an analog delay circuit to align the delays of the input signal in the feedforward and forward paths. A combiner subtracts the output of the analog delay of the forward path from the output of the sub-DAC in the feedforward path to generate a residue signal. Devices and methods disclosed herein are based on recognition that, if the errors introduced by the sub-DAC are known, they can be corrected in the digital domain during reconstruction, achieving superior NSD and distortion performance compared to conventional approaches.Type: ApplicationFiled: October 24, 2022Publication date: March 7, 2024Applicant: Analog Devices International Unlimited CompanyInventors: Sharvil Pradeep PATIL, Asha GANESAN, Hajime SHIBATA, Donald W. PATERSON, Haiyang ZHU
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Patent number: 11652491Abstract: Mechanisms for reducing or eliminating a quantization error caused by a quantizer of a continuous-time (CT) residue generation system are disclosed. In particular, systems and methods described herein are based on using a dither generation and injection circuit that can perform a high-pass filtering of the additive dither signal (i.e., a high-pass shaped dither signal). Using high-pass shaped dither signals is expected to improve quantizer linearity without significantly reducing the available error correction range. The applied dither may be particularly effective at minimizing signal-dependent distortion in ADC output spectrum caused by the quantizer when the quantization error cancellation accuracy may be insufficient.Type: GrantFiled: July 30, 2021Date of Patent: May 16, 2023Assignee: Analog Devices International Unlimited CompanyInventors: Victor Kozlov, Donald W. Paterson, Sharvil Pradeep Patil, Hajime Shibata
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Patent number: 11563442Abstract: Calibration of continuous-time (CT) residue generation systems can account and compensate for mismatches in magnitude and phase that may be caused by fabrication processes, temperature, and voltage variations. In particular, calibration may be performed by providing one or more known test signals as an input to a CT residue generation system, analyzing the output of the system corresponding to the known input, and then adjusting one or more parameters of a forward and/or a feedforward path of the system so that the difference in transfer functions of these paths may be reduced/minimized. Calibrating CT residue generation systems using test signals may help decrease the magnitude of the residue signals generated by such systems, and, consequently, advantageously increase an error correction range of such systems or of further stages that may use the residue signals as input.Type: GrantFiled: July 30, 2021Date of Patent: January 24, 2023Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Victor Kozlov, Sharvil Pradeep Patil, Hajime Shibata
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Publication number: 20220045687Abstract: Calibration of continuous-time (CT) residue generation systems can account and compensate for mismatches in magnitude and phase that may be caused by fabrication processes, temperature, and voltage variations. In particular, calibration may be performed by providing one or more known test signals as an input to a CT residue generation system, analyzing the output of the system corresponding to the known input, and then adjusting one or more parameters of a forward and/or a feedforward path of the system so that the difference in transfer functions of these paths may be reduced/minimized. Calibrating CT residue generation systems using test signals may help decrease the magnitude of the residue signals generated by such systems, and, consequently, advantageously increase an error correction range of such systems or of further stages that may use the residue signals as input.Type: ApplicationFiled: July 30, 2021Publication date: February 10, 2022Applicant: Analog Devices International Unlimited CompanyInventors: Victor KOZLOV, Sharvil Pradeep PATIL, Hajime SHIBATA
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Publication number: 20220045686Abstract: Mechanisms for reducing or eliminating a quantization error caused by a quantizer of a continuous-time (CT) residue generation system are disclosed. In particular, systems and methods described herein are based on using a dither generation and injection circuit that can perform a high-pass filtering of the additive dither signal (i.e., a high-pass shaped dither signal). Using high-pass shaped dither signals is expected to improve quantizer linearity without significantly reducing the available error correction range. The applied dither may be particularly effective at minimizing signal-dependent distortion in ADC output spectrum caused by the quantizer when the quantization error cancellation accuracy may be insufficient.Type: ApplicationFiled: July 30, 2021Publication date: February 10, 2022Applicant: Analog Devices International Unlimited CompanyInventors: Victor KOZLOV, Donald W. PATERSON, Sharvil Pradeep PATIL, Hajime SHIBATA
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Patent number: 11218158Abstract: In one aspect, a transfer function (TF) estimation circuit configured to generate an estimate of a TF undergone by signals between an input of a digital-to-analog converter (DAC) of a feedforward path of a continuous-time (CT) stage of an analog-to-digital converter (ADC) and an output of a backend ADC of the ADC is disclosed. The TF estimation circuit includes one or more circuits configured to generate a first cross-correlation output by cross-correlating digital versions of signals based on a test signal provided to the CT stage and an output signal of the backend ADC, generate a second cross-correlation output by cross-correlating digital versions of signals based on the test signal and an output signal of a quantizer of the feedforward path of the CT stage, and generate the estimate of the TF based on the first and second cross-correlation outputs.Type: GrantFiled: January 21, 2021Date of Patent: January 4, 2022Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Sharvil Pradeep Patil, Donald W. Paterson, Prawal Man Shrestha, Asha Ganesan, Yue Yin, Zhao Li, Victor Kozlov, Hajime Shibata
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Patent number: 11133814Abstract: An example residue generation arrangement for a continuous time or hybrid ADC includes a delay circuit having a cascade of analog delay sections, each section to provide a respective delay to an analog input signal, thus providing a delayed analog input signal at the output of the delay circuit. The delay circuit further includes a selector, configured to select an input or an output of one of the delay sections to provide as an input signal to a quantizer of a feedforward path. The quantizer may generate a digital input to a DAC of the feedforward path based on the output of the selector, and the DAC may generate a feedforward path analog output based on the digital signal generated by the quantizer. The arrangement further includes a summation node, configured to generate a residue signal based on the delayed analog input and the feedforward path analog output.Type: GrantFiled: December 3, 2020Date of Patent: September 28, 2021Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Sharvil Pradeep Patil, Kimo Tam, Hajime Shibata
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Patent number: 10218369Abstract: Disclosed herein are some continuous time systems and methods. Some of the disclosed systems and methods use a continuous-time analog-to-digital converter (ADC) configured to receive an analog input and to generate an ADC output, a continuous-time digital signal processor configured to receive the ADC output and generate one or more digital outputs, one or more digital-to-analog converters configured to receive the one or more digital outputs, each digital-to-analog converter configured to receive a corresponding digital output and generate an analog output, and an adder configured to receive the analog outputs of the one or more digital-to-analog converters and to generate a summed analog output.Type: GrantFiled: November 17, 2017Date of Patent: February 26, 2019Assignee: The Trustees of Columbia University in the City of New YorkInventors: Sharvil Pradeep Patil, Yannis Tsividis, Yu Chen
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Patent number: 10187075Abstract: Residue generation systems for use in continuous-time and hybrid ADCs are described. An exemplary system includes a filter, e.g. a FIR filter, for generating a filtered analog output based on an analog input, a quantizer for generating a digital input to a feedforward DAC based on the filtered analog output generated by the filter, a feedforward DAC for generating a feedforward path analog output based on the digital input generated by the quantizer, and a subtractor for generating a residue signal based on the feedforward path analog output. Providing a filter that filters the analog input before it is quantized advantageously allows blockers to be attenuated before they are sampled and aliased by the quantizer. At least some of the residue generation systems described herein may be implemented with relatively small design and power dissipation overheads.Type: GrantFiled: May 8, 2018Date of Patent: January 22, 2019Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANYInventors: Sharvil Pradeep Patil, Hajime Shibata, Yunzhi Dong, David Nelson Alldred, Frank Murden, Lawrence A. Singer
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Patent number: 10181860Abstract: A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.Type: GrantFiled: October 26, 2017Date of Patent: January 15, 2019Assignee: Analog Devices Global Unlimited CompanyInventors: Sharvil Pradeep Patil, Hajime Shibata, Wenhua William Yang, David Nelson Alldred, Yunzhi Dong, Gabriele Manganaro, Kimo Tam
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Publication number: 20180138918Abstract: Disclosed herein are some continuous time systems and methods. Some of the disclosed systems and methods use a continuous-time analog-to-digital converter (ADC) configured to receive an analog input and to generate an ADC output, a continuous-time digital signal processor configured to receive the ADC output and generate one or more digital outputs, one or more digital-to-analog converters configured to receive the one or more digital outputs, each digital-to-analog converter configured to receive a corresponding digital output and generate an analog output, and an adder configured to receive the analog outputs of the one or more digital-to-analog converters and to generate a summed analog output.Type: ApplicationFiled: November 17, 2017Publication date: May 17, 2018Inventors: Sharvil Pradeep Patil, Yannis Tsividis, Yu Chen
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Patent number: 9344107Abstract: The invention concerns an analog to digital conversion and filtering circuit comprising: an input for receiving an analog input signal; an asynchronous continuous-time analog to digital converter adapted to generate, based on the analog input signal, a digital continuous-time signal; a feedback path comprising a digital continuous-time filter adapted to generate a filtered signal to be combined with the analog input signal, the digital continuous-time filter being adapted to generate the filtered signal by: filtering out at least one first frequency range of the digital continuous-time signal; and amplifying at least one second frequency range of the digital continuous-time signal.Type: GrantFiled: June 12, 2015Date of Patent: May 17, 2016Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE, THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORKInventors: Dominique Morche, Alin Ratiu, Sharvil Pradeep Patil, Yannis Tsividis
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Patent number: 9300315Abstract: A programmable, quantization error spectral shaping, alias-free asynchronous analog-to-digital converter (ADC) is provided. The ADC can be used for clock-less, continuous-time digital signal processing in receivers with modest Signal to Noise-plus-Distortion Ratio (SNDR) requirements and a tight power budget.Type: GrantFiled: June 12, 2015Date of Patent: March 29, 2016Assignees: The Trustees of Columbia University in the City of New York, COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Sharvil Pradeep Patil, Yannis Tsividis, Dominique Morche, Alin Ratiu
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Publication number: 20150365098Abstract: A programmable, quantization error spectral shaping, alias-free asynchronous analog-to-digital converter (ADC) is provided. The ADC can be used for clock-less, continuous-time digital signal processing in receivers with modest Signal to Noise-plus-Distortion Ratio (SNDR) requirements and a tight power budget.Type: ApplicationFiled: June 12, 2015Publication date: December 17, 2015Inventors: Sharvil Pradeep PATIL, Yannis TSIVIDIS, Dominique MORCHE, Alin RATIU
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Patent number: 9071257Abstract: The derivative of an input signal is level-crossing-sampled and the resulting samples are transmitted. At the receiver, the resulting samples are fed to a zero-order hold followed by an integrator, which results in piecewise-linear reconstruction. The systems and methods are further refined to reduce the number of samples generated per unit of time, compared to methods based on zero-order-hold reconstruction, for a given signal-to-error ratio, without significant hardware overhead.Type: GrantFiled: July 9, 2014Date of Patent: June 30, 2015Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORKInventors: Sharvil Pradeep Patil, Yannis Tsividis, Pablo Martinez Nuevo
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Publication number: 20150015429Abstract: Systems and methods for level-crossing sampling and reconstruction technique are disclosed. The derivative of the input signal is level-crossing-sampled, and the resulting samples are transmitted. At the receiver, these samples are fed to a zero-order hold followed by an integrator, which results in piecewise-linear reconstruction. The disclosed systems and methods are further refined to reduce the number of samples generated per unit of time, compared to methods based on zero-order-hold reconstruction, for a given signal-to-error ratio, without significant hardware overhead.Type: ApplicationFiled: July 9, 2014Publication date: January 15, 2015Inventors: Sharvil Pradeep PATIL, Yannis TSIVIDIS, Pablo MARTINEZ NUEVO
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Patent number: D797920Type: GrantFiled: April 22, 2014Date of Patent: September 19, 2017Assignee: GLENMARK PHARMACEUTICALS LIMITEDInventors: Taranpreet Singh Lamba, Pradeep Patil, Rajneesh Shrivastava, Mayank Gupta, Karsten Nielsen, Neal Anderson, Ryan Hall, Saad Chaudry, Alex Garfield, Ben Clement
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Patent number: D804015Type: GrantFiled: April 22, 2014Date of Patent: November 28, 2017Assignee: GLENMARK PHARMACEUTICALS LIMITEDInventors: Taranpreet Singh Lamba, Pradeep Patil, Lai Chiu Tang