Patents by Inventor Pradeep PERIASAMY

Pradeep PERIASAMY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Decoded register outputs enabling test clock to selected asynchronous domains
    Patent number: 8479068
    Abstract: A system, circuit, and device for asynchronously scan capturing multi-clock domains. A system includes a shift register configured to process select data for selecting a clock domain at a time in response to a scan capture pulse and a one-hot n-to-2n decoder connected to the shift register and configured to generate one-hot code based on the select data. The system also includes integrated clock gating cells connected to the one-hot n-to-2n decoder, where the scan capture pulse is applied to each one of the integrated clock gating cells, and where only one of the integrated clock gating cells associated with the clock domain is enabled when the one-hot code is processed by the integrated clock gating cells. Further, the system includes multiplexers connected to the integrated clock gating cells, where the multiplexers are configured to forward the scan capture pulse to the clock domain.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: July 2, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Pradeep Periasamy, Anand Bhat, Tamilselvi Natarajan
  • SYSTEM, CIRCUIT, AND DEVICE FOR ASYNCHRONOUSLY SCAN CAPTURING MULTI-CLOCK DOMAINS
    Publication number: 20110276849
    Abstract: A system, circuit, and device for asynchronously scan capturing multi-clock domains. A system includes a shift register configured to process select data for selecting a clock domain at a time in response to a scan capture pulse and a one-hot n-to-2n decoder connected to the shift register and configured to generate one-hot code based on the select data. The system also includes integrated clock gating cells connected to the one-hot n-to-2n decoder, where the scan capture pulse is applied to each one of the integrated clock gating cells, and where only one of the integrated clock gating cells associated with the clock domain is enabled when the one-hot code is processed by the integrated clock gating cells. Further, the system includes multiplexers connected to the integrated clock gating cells, where the multiplexers are configured to forward the scan capture pulse to the clock domain.
    Type: Application
    Filed: May 10, 2010
    Publication date: November 10, 2011
    Inventors: Pradeep PERIASAMY, Anand BHAT, Tamilselvi NATARAJAN