Patents by Inventor Pradeep Rajagopal

Pradeep Rajagopal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10096701
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
  • Patent number: 8748298
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
  • Patent number: 8368117
    Abstract: Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the III-nitride material region(s) may be essentially eliminated. The presence of a strain-absorbing layer underlying the III-nitride material region(s) and/or processing conditions can contribute to achieving the low screw dislocation densities. In some embodiments, the III-nitride material region(s) having low dislocation densities include a gallium nitride material region which functions as the active region of the device. The low screw dislocation densities of the active device region (e.g., gallium nitride material region) can lead to improved properties (e.g.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: February 5, 2013
    Assignee: International Rectifier Corporation
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
  • Patent number: 7994540
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: August 9, 2011
    Assignee: International Rectifier Corporation
    Inventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Jr., Allen W. Hanson, Jerry W. Johnson, Kevin J. Linthicum, Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Sameer Singhal, Robert J. Therrien, Andrei Vescan
  • Publication number: 20100295056
    Abstract: Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the III-nitride material region(s) may be essentially eliminated. The presence of a strain-absorbing layer underlying the III-nitride material region(s) and/or processing conditions can contribute to achieving the low screw dislocation densities. In some embodiments, the III-nitride material region(s) having low dislocation densities include a gallium nitride material region which functions as the active region of the device. The low screw dislocation densities of the active device region (e.g., gallium nitride material region) can lead to improved properties (e.g.
    Type: Application
    Filed: March 29, 2010
    Publication date: November 25, 2010
    Applicant: Nitronex Corporation
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
  • Patent number: 7791106
    Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: September 7, 2010
    Assignee: Nitronex Corporation
    Inventors: Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Kevin J. Linthicum
  • Patent number: 7745848
    Abstract: Gallium nitride material devices and methods associated with the devices are described. The devices may be designed to provide enhanced thermal conduction and reduced thermal resistance. The increased thermal conduction through and out of the gallium nitride devices enhances operability of the devices, including providing excellent RF operation, reliability, and lifetime.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: June 29, 2010
    Assignee: Nitronex Corporation
    Inventors: Pradeep Rajagopal, Chul H. Park, Craig E. Strautin
  • Patent number: 7687827
    Abstract: Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the III-nitride material region(s) may be essentially eliminated. The presence of a strain-absorbing layer underlying the III-nitride material region(s) and/or processing conditions can contribute to achieving the low screw dislocation densities. In some embodiments, the III-nitride material region(s) having low dislocation densities include a gallium nitride material region which functions as the active region of the device. The low screw dislocation densities of the active device region (e.g., gallium nitride material region) can lead to improved properties (e.g.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: March 30, 2010
    Assignee: Nitronex Corporation
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
  • Publication number: 20100019850
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 28, 2010
    Applicant: Nitronex Corporation
    Inventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, JR., Allen W. Hanson, Jerry W. Johnson, Kevin J. Linthicum, Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Sameer Singhal, Robert J. Therrien, Andrei Vescan
  • Patent number: 7569871
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: August 4, 2009
    Assignee: Nitronex Corporation
    Inventors: Walter H. Nagy, Jerry Wayne Johnson, Edwin Lanier Piner, Pradeep Rajagopal, John Claassen Roberts, Sameer Singhal, Robert Joseph Therrien, Andrei Vescan, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Allen W. Hanson, Kevin J. Linthicum
  • Publication number: 20080246058
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 9, 2008
    Applicant: Nitronex Corporation
    Inventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Allen W. Hanson, Jerry W. Johnson, Kevin J. Linthicum, Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Sameer Singhal, Robert J. Therrien, Andrei Vescan
  • Publication number: 20080200013
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 21, 2008
    Applicant: Nitronex Corporation
    Inventors: Edwin Lanier Piner, John Claassen Roberts, Pradeep Rajagopal
  • Publication number: 20080182393
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Application
    Filed: January 31, 2008
    Publication date: July 31, 2008
    Applicant: Nitronex Corporation
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
  • Patent number: 7378684
    Abstract: An underlying gallium nitride layer on a silicon carbide substrate is masked with a mask that includes an array of openings therein, and the underlying gallium nitride layer is etched through the array of openings to define posts in the underlying gallium nitride layer and trenches therebetween. The posts each include a sidewall and a top having the mask thereon. The sidewalls of the posts are laterally grown into the trenches to thereby form a gallium nitride semiconductor layer. During this lateral growth, the mask prevents nucleation and vertical growth from the tops of the posts. Accordingly, growth proceeds laterally into the trenches, suspended from the sidewalls of the posts. The sidewalls of the posts may be laterally grown into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: May 27, 2008
    Assignee: North Carolina State University
    Inventors: Kevin J. Linthicum, Thomas Gehrke, Darren B. Thomson, Eric P. Carlson, Pradeep Rajagopal, Robert F. Davis
  • Publication number: 20080116456
    Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.
    Type: Application
    Filed: February 1, 2008
    Publication date: May 22, 2008
    Applicant: Nitronex Corporation
    Inventors: Edwin Piner, Pradeep Rajagopal, John Roberts, Kevin Linthicum
  • Patent number: 7365374
    Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: April 29, 2008
    Assignee: Nitronex Corporation
    Inventors: Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Kevin J. Linthicum
  • Patent number: 7352015
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: April 1, 2008
    Assignee: Nitronex Corporation
    Inventors: Edwin Lanier Piner, John Claassen Roberts, Pradeep Rajagopal
  • Patent number: 7352016
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: April 1, 2008
    Assignee: Nitronex Corporation
    Inventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Allen W. Hanson, Jerry Wayne Johnson, Kevin J. Linthicum, Edwin Lanier Piner, Pradeep Rajagopal, John Claassen Roberts, Sameer Singhal, Robert Joseph Therrien, Andrei Vescan
  • Patent number: 7339205
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: March 4, 2008
    Assignee: Nitronex Corporation
    Inventors: Edwin Lanier Piner, John C. Roberts, Pradeep Rajagopal
  • Patent number: 7247889
    Abstract: III-nitride material structures including silicon substrates, as well as methods associated with the same, are described. Parasitic losses in the structures may be significantly reduced which is reflected in performance improvements. Devices (such as RF devices) formed of structures of the invention may have higher output power, power gain and efficiency, amongst other advantages.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: July 24, 2007
    Assignee: Nitronex Corporation
    Inventors: Allen W. Hanson, John Claassen Roberts, Edwin L. Piner, Pradeep Rajagopal