Patents by Inventor Pradeep Ramesh

Pradeep Ramesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DETECTION ASSAYS
    Publication number: 20230272458
    Abstract: The present disclosure provides improved detection (e.g., diagnostic) assays that utilize a Cas protein collateral cleavage activity.
    Type: Application
    Filed: November 18, 2022
    Publication date: August 31, 2023
    Inventors: William Jeremy Blake, Xiang Li, Mary Katherine Wilson, Christine Marie Coticchia, Brendan John Manning, Pradeep Ramesh
  • IMPROVED DETECTION ASSAYS
    Publication number: 20230183783
    Abstract: The present disclosure provides improved detection (e.g., diagnostic) assays that utilize a Cas protein collateral cleavage activity.
    Type: Application
    Filed: January 27, 2021
    Publication date: June 15, 2023
    Inventors: William Jeremy Blake, Xiang Li, Mary Katherine Wilson, Christine Marie Coticchia, Brendan John Manning, Pradeep Ramesh
  • Chip package with staggered pin pattern
    Patent number: 11600544
    Abstract: A PCB having a first surface and a second surface includes a trench extending through the PCB, a plurality of conductive traces on one or more sidewalls of the trench. The plurality of conductive traces extends through the PCB and may be arranged in pairs across from one another along at least a portion of the length of the trench. A first set of conductive contacts are arranged in a first zig-zag pattern around a perimeter of the trench. A second set of conductive contacts are arranged in a second zig-zag pattern around the perimeter of the trench. In some cases, the first and second zig-zag patterns are arranged with respect to one another around the perimeter of the trench in an alternating fashion. A chip package is also disclosed having a pin arrangement that couples to the corresponding arrangement of conductive contacts on the PCB.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 7, 2023
    Assignee: Intel Corporation
    Inventors: Yogasundaram Chandiran, Geejagaaru Krishnamurthy Sandesh, Pradeep Ramesh, Ranjul Balakrishnan
  • CHIP PACKAGE WITH STAGGERED PIN PATTERN
    Publication number: 20200273765
    Abstract: A PCB having a first surface and a second surface includes a trench extending through the PCB, a plurality of conductive traces on one or more sidewalls of the trench. The plurality of conductive traces extends through the PCB and may be arranged in pairs across from one another along at least a portion of the length of the trench. A first set of conductive contacts are arranged in a first zig-zag pattern around a perimeter of the trench. A second set of conductive contacts are arranged in a second zig-zag pattern around the perimeter of the trench. In some cases, the first and second zig-zag patterns are arranged with respect to one another around the perimeter of the trench in an alternating fashion. A chip package is also disclosed having a pin arrangement that couples to the corresponding arrangement of conductive contacts on the PCB.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: INTEL CORPORATION
    Inventors: Yogasundaram Chandiran, Geejagaaru Krishnamurthy Sandesh, Pradeep Ramesh, Ranjul Balakrishnan