Patents by Inventor PRADEEP SREEDHAR

PRADEEP SREEDHAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907587
    Abstract: Storage devices are described herein that are capable of communicating with host-computing devices using multiple protocols. These Multi-Protocol Storage Devices (MPSDs) can be configured to utilize a persistent memory region (PMR) across a variety of protocols. Often, one of these protocols is the Non-Volatile Memory express (NVMe) protocol which provides for the ability to utilize and manage a PMR within the storage device. Other protocols may not have native support for PMR like the NVMe protocol does. Therefore, MPSDs are disclosed that may determine which protocol is in use in response to an initialization event and adjust the use of the PMR as needed based on the determined protocol. These adjustments may allow for the direct access of the PMR as an extension of general memory storage or may be configured to provide increased performance of the storage device overall. These storage devices may be hot-swappable between numerous host-computing systems.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Pradeep Sreedhar, Ramanathan Muthiah
  • Patent number: 11907573
    Abstract: A SD Card including, in one implementation, a memory array, a controller coupled to the memory array, and a bus for transferring data between the memory array and a host device in communication with the SD Card. The controller is configured to perform background maintenance operations on the memory array during execution of a read command received from the host device.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Pradeep Sreedhar, Deepak Naik, Bala Siva Kumar Narala, Abhishek Shetty
  • Publication number: 20220405012
    Abstract: A SD Card including, in one implementation, a memory array, a controller coupled to the memory array, and a bus for transferring data between the memory array and a host device in communication with the SD Card. The controller is configured to perform background maintenance operations on the memory array during execution of a read command received from the host device.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 22, 2022
    Inventors: Pradeep Sreedhar, Deepak Naik, Bala Siva Kumar Narala, Abhishek Shetty
  • Publication number: 20220398046
    Abstract: Storage devices are described herein that are capable of communicating with host-computing devices using multiple protocols. These Multi-Protocol Storage Devices (MPSDs) can be configured to utilize a persistent memory region (PMR) across a variety of protocols. Often, one of these protocols is the Non-Volatile Memory express (NVMe) protocol which provides for the ability to utilize and manage a PMR within the storage device. Other protocols may not have native support for PMR like the NVMe protocol does. Therefore, MPSDs are disclosed that may determine which protocol is in use in response to an initialization event and adjust the use of the PMR as needed based on the determined protocol. These adjustments may allow for the direct access of the PMR as an extension of general memory storage or may be configured to provide increased performance of the storage device overall. These storage devices may be hot-swappable between numerous host-computing systems.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 15, 2022
    Inventors: Pradeep Sreedhar, Ramanathan Muthiah
  • Patent number: 10635580
    Abstract: Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kalpit Bordia, Raghavendra Gopalakrishnan, Sachin Krishna Kudva, Ashim Ranjan Saikia, Bhanushankar Doni Gurudath, Ramanathan Muthiah, Pradeep Sreedhar, Prashanth Reddy Enukonda, Ramkumar Ramamurthy
  • Publication number: 20200012595
    Abstract: Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 9, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: KALPIT BORDIA, RAGHAVENDRA GOPALAKRISHNAN, SACHIN KRISHNA KUDVA, ASHIM RANJAN SAIKIA, BHANUSHANKAR DONI GURUDATH, RAMANATHAN MUTHIAH, PRADEEP SREEDHAR, PRASHANTH REDDY ENUKONDA, RAMKUMAR RAMAMURTHY