Abstract: Disclosed are approaches for to fabricating memory device channel holes using a doped film layer. One approach may include providing a substrate and forming a vertical stack over the substrate, wherein the vertical stack includes a plurality of alternating material layers. The method may further include forming a channel hole through the vertical stack, forming an oxide-nitride-oxide layer along a sidewall of the channel hole, forming a silicon layer over the oxide-nitride-oxide layer, forming an etch stop layer over the silicon layer, forming a fluorine-doped silicon layer over the etch step layer, and annealing the vertical stack.

Abstract: Disclosed are approaches for direct wordline contact formation for 3-D NAND devices. One method may include providing a film stack including a plurality of alternating first layers and second layers, and forming a plurality of contact openings in the film stack, wherein each contact opening is formed to a different etch depth relative to an upper surface of the film stack. The method may further include depositing a liner over the film stack including within each of the contact openings, removing the first layers to form a plurality of wordline openings in the film stack, and forming a plurality of wordlines by depositing a first conductive material within the wordline openings. The method may further include removing the liner from a bottom of each contact opening, and depositing a second conductive material within the contact openings to form a plurality of wordline contacts.

Abstract: Disclosed are approaches for fabricating 3D NAND flash memory structures including hollow epitaxial channels. One approach for fabricating a 3D NAND memory structure may include forming a plurality of alternating material layers arranged in a vertical stack on a substrate, etching a channel hole that extends through the plurality of alternating material layers to the substrate, and forming a tunneling layer around the channel hole contacting the plurality of alternating material layers. The method may further include forming a channel liner along the tunneling layer, forming a core gap material within the channel liner, removing the channel liner from the channel hole, and epitaxially growing a hollow epitaxial silicon core from the substrate through the channel hole, between the tunneling layer and the core gap material.

Abstract: Disclosed are approaches for direct wordline contact formation for 3D NAND devices. One method may include providing a first film stack comprising a first plurality of alternating first layers and second layers, and forming a first plurality of contact openings in the first film stack, wherein each contact opening is formed to a different etch depth. The method may further include forming a sacrificial gapfill within the first plurality of contact openings, and forming a second film stack atop the first film stack, wherein the second film stack comprises a second plurality of alternating first layers and second layers. The method may further include forming a second plurality of contact openings in the second film stack, wherein a first set of contact openings of the second plurality of contact openings extends to the sacrificial gapfill, and removing the sacrificial gapfill from the first plurality of contact openings.

Abstract: A method may include generating a residual curvature map for a substrate, the residual curvature map being based upon a measurement of the substrate. The method may include generating a dose map based upon the residual curvature map, the dose map being for processing the substrate using a patterning energy source. The method may include applying the dose map to process the substrate using the patterning energy source, wherein the dose map is applied by performing a plurality of exposures of the substrate to the patterning energy source, at a plurality of different twist angles.

Abstract: A method may include generating a residual curvature map for a substrate, the residual curvature map being based upon a measurement of a surface of the substrate. The method may include generating a dose map based upon the residual curvature map, the dose map being for processing the substrate using a patterning energy source; and applying the dose map to process the substrate using the patterning energy source.

Abstract: Methods of forming a nanosheet field effect transistor (FET) device with reduced source/drain contact resistance are provided herein. In some embodiments, a method of forming an FET device includes: etching a nanosheet stack of the nanosheet FET device to form a plurality of first source/drain regions and a plurality of second source/drain regions, the nanosheet stack comprising alternating layers of nanosheet channel layers and sacrificial nanosheet layers; depositing a silicide layer in the plurality of first source/drain regions at ends of the nanosheet channel layers via a selective silicidation process to control a length of the nanosheet channel layers between the first source/drain regions; and performing a metal fill process to fill the plurality of first source/drain regions, wherein the metal fill extends from a lowermost nanosheet channel layer to above an uppermost nanosheet channel layer to facilitate the reduced source/drain contact resistance.

Abstract: Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

Abstract: The methods and systems disclosed here detect edges of top-down images of respective cross-sections of an array of high-aspect-ratio (HAR) features. The respective cross sections are at various depths of a HAR feature along a longitudinal direction. The detected edges are re-sampled in a spatial domain at a target angular resolution. The re-sampled edges are represented as a corresponding set of harmonics in a frequency domain, each set of harmonics preserving characteristic information about a respective cross-section of the HAR feature at a certain depth. A plurality of cross-sections at the various depths of the HAR feature are reconstructed by analyzing the corresponding sets of harmonics in the frequency domain. A 3D profile of the HAR feature is generated by stitching the plurality of re-constructed cross-sections at the various depths of the HAR feature.

Abstract: The methods and systems disclosed here detect edges of top-down images of respective cross-sections of an array of high-aspect-ratio (HAR) features. The respective cross sections are at various depths of a HAR feature along a longitudinal direction. The detected edges are re-sampled in a spatial domain at a target angular resolution. The re-sampled edges are represented as a corresponding set of harmonics in a frequency domain, each set of harmonics preserving characteristic information about a respective cross-section of the HAR feature at a certain depth. A plurality of cross-sections at the various depths of the HAR feature are reconstructed by analyzing the corresponding sets of harmonics in the frequency domain. A 3D profile of the HAR feature is generated by stitching the plurality of re-constructed cross-sections at the various depths of the HAR feature.

Abstract: The methods and systems disclosed here leverage currently available reliable top down imaging techniques used by SEMs and use computational methods to synthesize accurate 3D profiles of features of high aspect ratio structures in a device. Radial cross-sectional profiles obtained from different locations along the lateral direction at different heights/depths are stitched together to create one composite 3D profile of the HAR feature.

Abstract: The methods and systems disclosed here leverage currently available reliable top down imaging techniques used by SEMs and use computational methods to synthesize accurate 3D profiles of features of high aspect ratio structures in a device. Radial cross-sectional profiles obtained from different locations along the lateral direction at different heights/depths are stitched together to create one composite 3D profile of the HAR feature.

Abstract: A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample.

Abstract: An apparatus for fixing a wafer, including a chuck having a surface, a plurality of through bores in the chuck extending through the surface of the chuck, a fixed vacuum bellows, and a plurality of floating air bearings, wherein the fixed vacuum bellows and a respective floating air bearing of the plurality of floating air bearings are each individually arranged in separate through bores of the plurality of through bores and elevationally above the surface of the chuck.

Abstract: A lithography system includes an illumination source and a set of projection optics. The illumination source directs a beam of illumination from an off-axis illumination pole to a pattern mask. The pattern mask includes a set of pattern elements to generate a set of diffracted beams including illumination from the illumination pole. At least two diffracted beams of the set of diffracted beams received by the set of projection optics are asymmetrically distributed in a pupil plane of the set of projection optics. The at least two diffracted beams of the set of diffracted beams are asymmetrically incident on the sample to form a set of fabricated elements corresponding to an image of the set of pattern elements. The set of fabricated elements on the sample includes one or more indicators of a location of the sample along an optical axis of the set of projection optics.

Abstract: A lithography system includes an illumination source, projection optical elements, and a pattern mask. The illumination source includes one or more illumination poles. The pattern mask includes a set of focus-sensitive mask elements distributed with a pitch and, is configured to diffract illumination from the one or more illumination poles. The pitch may be selected such that two diffraction orders of illumination associated with each of the one or more illumination poles are asymmetrically distributed in a pupil plane of the projection optical elements. Further, the projection optical elements may expose a sample with an image of the set of focus-sensitive pattern mask elements based on the two diffraction orders of illumination associated with each of the one or more illumination poles such that one or more printing characteristics is indicative of a position of the sample within a focal volume of the projection optical elements.

Abstract: A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample.

Abstract: A lithography system includes an illumination source, one or more projection optical elements, and a pattern mask. The illumination source includes one or more illumination poles. The pattern mask includes a set of focus-sensitive mask elements periodically distributed with a pitch, wherein the set of focus-sensitive mask elements is configured to diffract illumination from the one or more illumination poles. The pitch is selected such that two diffraction orders of illumination associated with each of the one or more illumination poles are asymmetrically distributed in a pupil plane of the one or more projection optical elements. Further, the one or more projection optical elements are configured to expose a sample with an image of the set of focus-sensitive pattern mask elements based on the two diffraction orders of illumination associated with each of the one or more illumination poles.

Abstract: A lithography system includes an illumination source and a set of projection optics. The illumination source directs a beam of illumination from an off-axis illumination pole to a pattern mask. The pattern mask includes a set of pattern elements to generate a set of diffracted beams including illumination from the illumination pole. At least two diffracted beams of the set of diffracted beams received by the set of projection optics are asymmetrically distributed in a pupil plane of the set of projection optics. The at least two diffracted beams of the set of diffracted beams are asymmetrically incident on the sample to form a set of fabricated elements corresponding to an image of the set of pattern elements. The set of fabricated elements on the sample includes one or more indicators of a location of the sample along an optical axis of the set of projection optics.

Abstract: An apparatus tor fixing a wafer, including a chuck having a surface, a plurality of through bores in the chuck extending through the surface of the chuck, a fixed vacuum bellows, and a plurality of floating air bearings, wherein the fixed vacuum bellows and a respective floating air bearing of the plurality of floating air bearings are each individually arranged in separate through bores of the plurality of through bores and elevationally above the surface of the chuck.