Patents by Inventor Pradeep Yadav

Pradeep Yadav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113525
    Abstract: A method and aircraft power distribution system includes a power distribution bus supplying power along an electrical line, a primary communication module including a primary transceiver and a primary controller, and a plurality of secondary communication modules including a secondary transceiver communicatively coupled to the primary transceiver and a secondary controller communicatively coupled to the secondary transceiver.
    Type: Application
    Filed: February 24, 2023
    Publication date: April 4, 2024
    Inventors: Joginder Yadav, Pradeep V
  • Patent number: 11188696
    Abstract: An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 30, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Dhuria, Sri Harsha Venkata Pothukuchi, Pradeep Yadav, Pawan Kulshreshtha, Igor Keller, Sharad Mehrotra, Jean Pierre Hiol, Krishna Prasad Belkhale
  • Patent number: 10289774
    Abstract: Various embodiments describe performing static timing analysis (STA) on a circuit design such that delay timing calculation results generated by an STA on the circuit design can be reused by subsequent STAs on the circuit design in place of performing a set of delay timing calculations on the circuit design.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc
    Inventors: Pradeep Yadav, Ratnakar Goyal, Prashant Sethia, Manuj Verma
  • Patent number: 9529962
    Abstract: The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: December 27, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Dhuria, Pradeep Yadav, Manuj Verma, Naresh Kumar, Prashant Sethia
  • Patent number: 9384310
    Abstract: A system and method for performing multi-mode multi-corner (MMMC) analysis such that multiple views or conditions can be analyzed together to improve runtime by taking advantage of common steps of analysis in different corners. Views are clustered based on their similarity to one another to take advantage of calculations and other tasks that may be shared between views during timing analysis. Then, during timing analysis, each net in the design is analyzed for each view.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 5, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Igor Keller, Jijun Chen, Pradeep Yadav
  • Patent number: 8863052
    Abstract: A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level hierarchical circuit design for timing analyses and pessimism removal to arrive at realistic timing characteristics. The structural weights are particularly helpful in an AOCV-type pessimism removal post-process.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: October 14, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Dhuria, Naresh Kumar, Umesh Gupta, Pradeep Yadav, Prashant Sethia
  • Publication number: 20090130042
    Abstract: The invention is directed to a topical composition suitable to control sweat. The composition comprises a low HLB lipid and a silicone oil whereby the composition has at least one metastable phase formed during topical application to the skin. The composition does not interfere with thermoregulation of the body, and yields a quantifiable cooling effect when applied.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 21, 2009
    Inventors: Teanoosh Moaddel, Pradeep Yadav, Alexander Lips
  • Publication number: 20080254074
    Abstract: A skin care composition for regulating sebum flow from sebocytes is described. The composition comprises spheroids, and optionally, thickening agents and when a spheroid and sebum mixture is made upon application, the resulting mixture leaves a pleasant, silky and powdery sensation.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 16, 2008
    Applicant: CONOPCO, INC., D/B/A UNILEVER
    Inventors: Anne Dussaud, Pradeep Yadav