Patents by Inventor Pradeep Yelehanka
Pradeep Yelehanka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9272899Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.Type: GrantFiled: January 7, 2015Date of Patent: March 1, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Huamao Lin, Pradeep Yelehanka
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Publication number: 20150115453Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.Type: ApplicationFiled: January 7, 2015Publication date: April 30, 2015Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Huamao LIN, Pradeep YELEHANKA
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Patent number: 8940616Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.Type: GrantFiled: July 27, 2012Date of Patent: January 27, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Huamao Lin, Pradeep Yelehanka
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Publication number: 20140030847Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Huamao LIN, Pradeep YELEHANKA
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Patent number: 8236678Abstract: A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.Type: GrantFiled: December 17, 2008Date of Patent: August 7, 2012Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Ramachandramurthy Pradeep Yelehanka, Shailendra Mishra, Sripad Nagarad
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Patent number: 7879732Abstract: A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.Type: GrantFiled: December 18, 2007Date of Patent: February 1, 2011Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Xiang Hu, Hai Cong, Pradeep Yelehanka, Mei Sheng Zhou
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Publication number: 20100148269Abstract: A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Ramachandramurthy Pradeep YELEHANKA, Shailendra MISHRA, Sripad NAGARAD
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Publication number: 20090156010Abstract: A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Inventors: Xiang Hu, Hai Cong, Pradeep Yelehanka, Mei Sheng Zhou
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Patent number: 7323736Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.Type: GrantFiled: May 22, 2006Date of Patent: January 29, 2008Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Pradeep Yelehanka, Sanford Chu, Chit Hwei Ng, Jia Zhen, Purakh Verma
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Publication number: 20060281253Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: ApplicationFiled: August 22, 2006Publication date: December 14, 2006Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Pradeep Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
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Publication number: 20060220110Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.Type: ApplicationFiled: May 30, 2006Publication date: October 5, 2006Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Tommy Lai, Pradeep Yelehanka, Jia Zhen Zheng, Weining Li
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Publication number: 20060214185Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.Type: ApplicationFiled: June 6, 2006Publication date: September 28, 2006Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Jia Zhen Zheng, Weining Li, Tze Ho Simon Chan, Pradeep Yelehanka
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Patent number: 7060193Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.Type: GrantFiled: July 5, 2002Date of Patent: June 13, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Pradeep Yelehanka, Sanford Chu, Chit Hwei Ng, Jia Zhen, Purakh Verma
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Publication number: 20050167664Abstract: An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.Type: ApplicationFiled: March 10, 2005Publication date: August 4, 2005Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Elgin Quek, Jia Zheng, Pradeep Yelehanka, Weining Li
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Patent number: 6884712Abstract: An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: GrantFiled: February 7, 2003Date of Patent: April 26, 2005Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Pradeep Yelehanka, Tong Qing Chen, Zhi Yong Han, Zhen Jia Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
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Publication number: 20050026343Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are then formed on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is formed from at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is formed from at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor being in contact with the thyristor.Type: ApplicationFiled: July 28, 2003Publication date: February 3, 2005Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Elgin Quek, Jia Zheng, Pradeep Yelehanka, Weining Li
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Publication number: 20030092281Abstract: A method for etching an organic bottom antireflective coating (OBARC) and a photoresist material in a single etching process. The method comprises the steps of etching the OBARC and trimming the photoresist material at the same time in an etching environment using a substantially isotropic etching operation. The etching environment including an etching chamber with a top electrode and a bottom electrode wherein a mixture of abrasive gases can flow therethrough. Using an endpoint detection test to determine when an exposed portion of OBARC has been removed, the exposed portion of OBARC being an area of OBARC without photoresist protection and exposed to the etching environment. Applying an over-etch step to trim the photoresist to a desired dimension where the time of the over-etch step being based on the percentage of an endpoint time and the process condition of the over-etch step being same as that of the endpoint step.Type: ApplicationFiled: November 13, 2001Publication date: May 15, 2003Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITEDInventors: Pradeep Yelehanka Ramachandramurthy, Jie Yu, Loh Wei Loong, Chen Tong Qing
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Patent number: 6093602Abstract: A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided overlying the substrate. A dielectric layer is deposited overlying the substrate and the narrowly spaced features. The dielectric layer is patterned to form openings between the narrowly spaced features for planned contacts to the surface of the substrate. A doped polysilicon layer is deposited overlying the dielectric layer and filling the openings. The doped polysilicon layer is etched down to the top surface of the narrowly spaced features. The doped polysilicon layer remains in the spaces between the narrowly spaced features. A polycide layer is formed overlying the narrowly spaced features and the doped polysilicon layer. The polycide layer and the doped polysilicon layer are patterned to complete the contacts and create the local interconnects of polycide, and the integrated circuit device is completed.Type: GrantFiled: July 16, 1999Date of Patent: July 25, 2000Assignee: Chartered Semiconductor Manufacturing CompanyInventors: Weining Li, Lin Yung Tao, Ramachandramurthy Pradeep Yelehanka, Tin Tin Wee