Patents by Inventor Pradip JADHAV

Pradip JADHAV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11863187
    Abstract: A circuit is provided. The circuit includes a first master stage, a second master stage, a first slave stage, a first slave stage, and a second slave stage. The first master stage includes a data input line. The second master stage includes an inverse data input line. The first slave stage is coupled to an output of the first master stage. The second slave stage is coupled to an output of the second master stage. The first slave stage generates an output signal during a rising edge of a clock cycle. The second slave stage generates an inverted output signal during the rising edge of the clock cycle. The output signal and the inverted output signal are available concurrently.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: January 2, 2024
    Assignee: Synopsys, Inc.
    Inventors: Pradip Jadhav, Michael McManus
  • Publication number: 20220399881
    Abstract: A circuit is provided. The circuit includes a first master stage, a second master stage, a first slave stage, a first slave stage, and a second slave stage. The first master stage includes a data input line. The second master stage includes an inverse data input line. The first slave stage is coupled to an output of the first master stage. The second slave stage is coupled to an output of the second master stage. The first slave stage generates an output signal during a rising edge of a clock cycle. The second slave stage generates an inverted output signal during the rising edge of the clock cycle. The output signal and the inverted output signal are available concurrently.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 15, 2022
    Applicant: Synopsys, Inc.
    Inventors: Pradip JADHAV, Michael McMANUS