Patents by Inventor Pradip Patel
Pradip Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10998075Abstract: A non-limiting example includes data storage circuitry. The data storage circuitry includes a built-in self-test (BIST) engine. The data storage circuitry includes a memory array including memory cells. The memory array is configured to store data based on a read-write vector associated with an address vector that includes memory addresses and according to a bit-write vector that defines bit-write enablement for the memory addresses. The memory array is configured to output a stored data vector. The data storage circuitry includes a selector configured to receive the bit-write vector, and to output a selected vector based on an initialization vector and a comparison vector based at least in part on the bit-write vector. The data storage circuitry includes a comparator configured to receive the stored data vector and the selected vector, and to output an error based on discrepancies between the stored data vector and the selected vector.Type: GrantFiled: September 11, 2019Date of Patent: May 4, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Daniel Rodko, Pradip Patel, Matthew Steven Hyde
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Patent number: 10971242Abstract: Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal.Type: GrantFiled: September 11, 2019Date of Patent: April 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Daniel Rodko, Pradip Patel
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Publication number: 20210074376Abstract: A non-limiting example includes data storage circuitry. The data storage circuitry includes a built-in self-test (BIST) engine. The data storage circuitry includes a memory array including memory cells. The memory array is configured to store data based on a read-write vector associated with an address vector that includes memory addresses and according to a bit-write vector that defines bit-write enablement for the memory addresses. The memory array is configured to output a stored data vector. The data storage circuitry includes a selector configured to receive the bit-write vector, and to output a selected vector based on an initialization vector and a comparison vector based at least in part on the bit-write vector. The data storage circuitry includes a comparator configured to receive the stored data vector and the selected vector, and to output an error based on discrepancies between the stored data vector and the selected vector.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Inventors: William Huott, Daniel Rodko, Pradip Patel, Matthew Steven Hyde
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Publication number: 20210074375Abstract: Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Inventors: William Huott, Daniel Rodko, Pradip Patel
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Patent number: 10890623Abstract: Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.Type: GrantFiled: September 4, 2019Date of Patent: January 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Yuen Chan, Pradip Patel, Daniel Rodko
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Patent number: 10593420Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.Type: GrantFiled: February 19, 2018Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Harry Barowski, Sheldon Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter
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Patent number: 10585023Abstract: A method of treating a biological sample, preferably a sample of blood or bodily fluids likely to contain one or more species of interest, and including a step of decomplexification by acoustophoresis (as well as associated systems, devices, substrates and connection devices).Type: GrantFiled: October 23, 2015Date of Patent: March 10, 2020Assignee: BIOMERIEUXInventors: Patrick Broyer, Pradip Patel, Nicole Pamme, Emilie Bisceglia
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Patent number: 10365191Abstract: A method for treating a biological sample, preferably a food sample which may contain one or more species of interest, including a step of decomplexification by acoustophoresis.Type: GrantFiled: October 23, 2015Date of Patent: July 30, 2019Assignee: BIOMERIEUXInventors: Patrick Broyer, Pradip Patel, Nicole Pamme, Jean-Claude Raymond
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Patent number: 10170199Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.Type: GrantFiled: February 19, 2018Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Harry Barowski, Sheldon Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter
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Patent number: 10079070Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.Type: GrantFiled: October 20, 2016Date of Patent: September 18, 2018Assignee: International Business Machines CorporationInventors: Harry Barowski, Sheldon Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter
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Publication number: 20180174666Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.Type: ApplicationFiled: February 19, 2018Publication date: June 21, 2018Inventors: Harry Barowski, Sheldon Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter
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Publication number: 20180151248Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.Type: ApplicationFiled: February 19, 2018Publication date: May 31, 2018Inventors: Harry Barowski, Sheldon Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter
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Patent number: 9983261Abstract: Aspects of present disclosure relate to an integrated circuit chip (chip), a method and a computer program product of testing the chip. The method of testing the chip may include: partitioning the chip into various partitions, loading built-in self-test (BIST) test instructions into BIST engine and initializing a current partition counter, performing BIST test on current partition, transmitting test results of the current partition of the chip to an external test data storage, checking whether current partition is the last partition, incrementing current partition counter, and returning to performing BIST on a next partition when current partition is not the last partition, and exiting BIST test when current partition is the last partition. The test results may be stored in one or more inactive storage elements of the chip. The number of partitions may include: one partition, a predetermined number of partitions, and a variable number of partitions.Type: GrantFiled: June 1, 2016Date of Patent: May 29, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William V. Huott, Thomas J. Knips, Pradip Patel, Daniel Rodko
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Publication number: 20180114585Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.Type: ApplicationFiled: October 20, 2016Publication date: April 26, 2018Inventors: Harry Barowski, Sheldon Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter
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Publication number: 20170350940Abstract: Aspects of present disclosure relate to an integrated circuit chip (chip), a method and a computer program product of testing the chip. The method of testing the chip may include: partitioning the chip into various partitions, loading built-in self-test (BIST) test instructions into BIST engine and initializing a current partition counter, performing BIST test on current partition, transmitting test results of the current partition of the chip to an external test data storage, checking whether current partition is the last partition, incrementing current partition counter, and returning to performing BIST on a next partition when current partition is not the last partition, and exiting BIST test when current partition is the last partition. The test results may be stored in one or more inactive storage elements of the chip. The number of partitions may include: one partition, a predetermined number of partitions, and a variable number of partitions.Type: ApplicationFiled: June 1, 2016Publication date: December 7, 2017Inventors: William V. Huott, Thomas J. Knips, Pradip Patel, Daniel Rodko
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Publication number: 20170315033Abstract: A method for treating a biological sample, preferably a food sample which may contain one or more species of interest, including a step of decomplexification by acoustophoresis.Type: ApplicationFiled: October 23, 2015Publication date: November 2, 2017Applicant: BIOMERIEUXInventors: Patrick BROYER, Pradip PATEL, Nicole PAMME, Jean-Claude RAYMOND
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Publication number: 20170241878Abstract: A method of treating a biological sample, preferably a sample of blood or bodily fluids likely to contain one or more species of interest, and including a step of decomplexification by acoustophoresis (as well as associated systems, devices, substrates and connection devices).Type: ApplicationFiled: October 23, 2015Publication date: August 24, 2017Applicant: BIOMERIEUXInventors: Patrick BROYER, Pradip PATEL, Nicole PAMME, Emilie BISCEGLIA
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Patent number: 9697910Abstract: An aspect includes a method of multi-match error detection in content addressable memory (CAM) testing. The method includes loading a content addressing row of a CAM section with a row test address word. Data value rows of a random access memory (RAM) section are loaded with unique test patterns in each of the data value rows having a same number of on-state bits per data value row. A row test is initiated to search for a matching content addressing row in the CAM section corresponding to the row test address word. A row test result is received as one or more data value rows from the RAM section identified as having a content addressing row in the CAM section that matches the row test. The row test result is compared to an aspect of one or more of the unique test patterns to determine whether the row test has failed.Type: GrantFiled: March 30, 2016Date of Patent: July 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William V. Huott, Pradip Patel, Daniel Rodko
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Patent number: 9627012Abstract: Aspects include a computer-implemented method for scanning data into a shift register. The method includes receiving, by a circuit, a data signal, wherein the data signal propagates in a first direction; and receiving, by the circuit, a clock signal, wherein the clock signal propagates in a second direction, wherein the second direction is in a reverse direction of the first direction.Type: GrantFiled: June 29, 2016Date of Patent: April 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William V. Huott, Norman K. James, Pradip Patel, Daniel Rodko
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Publication number: 20150079597Abstract: The present invention relates generally to the field of analysis, for example biological analysis. More specifically, the present invention relates to a method for capturing and concentrating at least one microorganism or at least one protein secreted by a microorganism that may be present in the sample placed in a container, the method including the following steps: a) in the container, bringing the sample into contact with a culture medium and a sponge capable of capturing the microorganism(s) or the protein(s) secreted by at least one microorganism to be detected, functionalized with a binding partner of at least one microorganism or of at least one secreted protein; b) placing the container in suitable conditions allowing growth of the microorganism or microorganisms; and c) repeatedly compressing and decompressing the sponge while it remains in contact with the medium.Type: ApplicationFiled: January 8, 2013Publication date: March 19, 2015Inventors: Jean-Pierre Flandrois, Jean-Claude Raymond, David Mosticone, Pradip Patel, Thierry Sofia