Abstract: The present teaching relates to dynamically generate a score floor model that provides a dynamically determined threshold metric to be used to select future bids that satisfy a first and second set of metrics. Feedback information is first received that relates to a plurality of bids previously submitted by a bidder to a publisher, wherein the feedback information indicates whether each of the plurality of bids has led to an impression. The first set of metrics specified by the publisher is obtained and the second set of metrics is retrieved. The score floor model with respect to the publisher is dynamically updated based on the feedback information as well as the first and second sets of metrics.

Abstract: The present teaching relates to dynamically generate a score floor model that provides a dynamically determined threshold metric to be used to select future bids that satisfy a first and second set of metrics. Feedback information is first received that relates to a plurality of bids previously submitted by a bidder to a publisher, wherein the feedback information indicates whether each of the plurality of bids has led to an impression. The first set of metrics specified by the publisher is obtained and the second set of metrics is retrieved. The score floor model with respect to the publisher is dynamically updated based on the feedback information as well as the first and second sets of metrics.

Abstract: A circuit may include a signal converter configured to convert a differential signal to a single-ended signal. The circuit may also include a biasing circuit configured to set a bias of the signal converter based on a feedback of the single-ended signal such that a voltage level of the single-ended signal is at a target voltage level.

Abstract: A clock multiplication and distribution system includes a first phase-lock-loop circuit, a second phase-lock-loop circuit, and a clock distribution network that electrically couples the first phase-lock-loop circuit and the second phase-lock-loop circuit. The first phase-lock-loop circuit may include a first feedback loop that includes a first integer divider circuit and may be configured to generate a first clock using a reference clock. A frequency of the first clock may be greater than a frequency of the reference clock. The second phase-lock-loop circuit may include a second feedback loop that includes a second integer divider circuit and may be configured to generate a second clock using the first clock. A frequency of the second clock may be greater than the frequency of the first clock.

Abstract: A circuit may include a signal converter configured to convert a differential signal to a single-ended signal. The circuit may also include a biasing circuit configured to set a bias of the signal converter based on a feedback of the single-ended signal such that a voltage level of the single-ended signal is at a target voltage level.

Abstract: A clock multiplication and distribution system includes a first phase-lock-loop circuit, a second phase-lock-loop circuit, and a clock distribution network that electrically couples the first phase-lock-loop circuit and the second phase-lock-loop circuit. The first phase-lock-loop circuit may include a first feedback loop that includes a first integer divider circuit and may be configured to generate a first clock using a reference clock. A frequency of the first clock may be greater than a frequency of the reference clock. The second phase-lock-loop circuit may include a second feedback loop that includes a second integer divider circuit and may be configured to generate a second clock using the first clock. A frequency of the second clock may be greater than the frequency of the first clock.

Abstract: A system configured to generate a signal with a random or pseudo-random frequency may include an oscillator and a signal generator. The oscillator may be configured to generate an oscillator signal. A frequency and a phase of the oscillator signal may be random or pseudo-random and may be based on a value of a received control signal. The signal generator may be configured to generate the control signal based on the oscillator signal and a seed state. The value of the control signal may be random or pseudo-random.

Abstract: A system configured to generate a signal with a random or pseudo-random frequency may include an oscillator and a signal generator. The oscillator may be configured to generate an oscillator signal. A frequency and a phase of the oscillator signal may be random or pseudo-random and may be based on a value of a received control signal. The signal generator may be configured to generate the control signal based on the oscillator signal and a seed state. The value of the control signal may be random or pseudo-random.

Abstract: The present disclosure relates to a method of optimizing via cutouts, including selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry selected to provide an extension region extending in the direction of the first differential trace. Additionally, the method includes the steps of selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region, and selecting a radial dimension of a first and second via cutout on a second ground reference layer adjacent to and between the first and second differential traces, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

Abstract: A system includes an array of comparators configured to convert an analog input to a digital output, a switch configured to adjust output bits of the digital output, and a control logic; the control logic is configured to initialize the switch and a direct-current source coupled to the analog input; the control logic is configured to increase the direct-current source in incremental steps of a minimal voltage value corresponding to the least significant bit of the digital output; and the control input is also configured to cause the switch to adjust one or more output bits of the digital output based at least in part on a value of the output bit corresponding to the current incremental step.

Abstract: The present disclosure relates to a method of optimizing via cutouts, including selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry selected to provide an extension region extending in the direction of the first differential trace. Additionally, the method includes the steps of selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region, and selecting a radial dimension of a first and second via cutout on a second ground reference layer adjacent to and between the first and second differential traces, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

Abstract: In one embodiment, a comparator of a Flash analog-to-digital converter (ADC) is calibrated in the background by switching the comparator to a feedback loop, determining the comparator's current reference level, and adjusting the comparator's reference level to a target reference level by charging a reference capacitor coupled the comparator.

Abstract: In one embodiment, a comparator of a Flash analog-to-digital converter (ADC) is calibrated in the background by switching the comparator to a feedback loop, determining the comparator's current reference level, and adjusting the comparator's reference level to a target reference level by charging a reference capacitor coupled the comparator.