Abstract: An integrated circuit is made by utilizing a delay and/or capacitance model and/or setup/hold time model which provides for the ability to isolate issues of transistor performance, metallization capacitance, metallization resistance, power supply voltage, and temperature for the individual design blocks that make up the integrated circuit. This is achieved by utilizing an equation representative of these performance characteristics as certain variables in the equation. The equation also has constants which are determined by first running the design blocks through a standard circuit simulator. The result is a different set of these constants for each design block. Various signal paths are made up of various design blocks so that each path can be analyzed by analyzing the performance of the individual blocks that make up the path. Thus, areas of improvement for the design blocks are more easily identified prior to actually making the integrated circuit.

Abstract: The invention relates to a new method of guidance for routing of nets in an integrated circuit model wherein all nets are first approximately routed, as with Steiner routing, and victim nets with functional delay noise above predetermined thresholds are identified. Each victim net is then detail routed. For each victim net detail routed, a set of least noise aggressive neighboring nets is selected. Segments of those neighboring nets are assigned tracks adjacent to the victim net in such a way as to maximize utilization of the victim net's neighboring tracks, thereby reducing noise induced on the victim net and maximizing use of available space on the semiconductor. The process is then repeated until there are no additional victim nets, at which point the remaining nets are detail routed.