Abstract: Aspects of the invention relate to techniques of layout decomposition for triple patterning lithography. Data of a coloring graph are derived from layout data for a layout design. The coloring graph is simplified through graph reduction and graph partitioning processes. The graph partitioning process comprises separating biconnected components. The graph partitioning process may further comprise separating subgraphs connected by one or two edges. Based on the simplified coloring graph, the layout design is decomposed to generate decomposition information. The decomposition process may comprise applying a heuristic method for coloring if needed. The decomposition information may comprise information of one or more layout regions that cannot be decomposed.

Abstract: Aspects of the invention relate to techniques of layout decomposition for triple patterning lithography. Data of a coloring graph are derived from layout data for a layout design. The coloring graph is simplified through graph reduction and graph partitioning processes. The graph partitioning process comprises separating biconnected components. The graph partitioning process may further comprise separating subgraphs connected by one or two edges. Based on the simplified coloring graph, the layout design is decomposed to generate decomposition information. The decomposition process may comprise applying a heuristic method for coloring if needed. The decomposition information may comprise information of one or more layout regions that cannot be decomposed.

Abstract: A typical post-out flow data path at the IC Fabrication has following major components of software based processing—Boolean operations before the application of resolution enhancement techniques (RET) and optical proximity correctin (OPC), the RET and OPC step [etch retargeting, sub-resolution assist feature insertion (SRAF) and OPC], post-OPCRET Boolean operations and sometimes in the same flow simulation based verification. There are two objectives that an IC Fabrication tapeout flow manager wants to achieve with the flow—predictable completion time and fastest turn-around time (TAT). At times they may be competing. An alternative method of providing target turnaround time and managing the priority of jobs while not doing any upfront resource modeling and resource planning is disclosed. The methodology systematically either meets the turnaround time need and potentially lets the user know if it will not as soon as possible.

Abstract: Layout design data is analyzed to identify both potential geometric element cuts in the design and instances of an application of a separation directive. Each of the identified separation directive instances and the identified cuts are assigned an analysis value, such as a weight value. The separation directive instances and the identified cuts then are ordered in a single list according to their analysis values. Each item on the list is then analyzed, to determine if the item can be implemented in the layout design data without creating a conflict in complementary pattern sets for using in a double-patterning lithographic technique. If a list item (either separation directive instance or identified cut) cannot be implemented without creating a conflict in one of the complementary patterns, then it is discarded from the list. After each of the list items has been analyzed, the remaining items are implemented in the design layout data.

Abstract: A system for resolving object address. A computer-implemented method for resolving addresses in a computing system includes dynamically assigning a library identifier to a database stored on a secondary storage medium and obtaining a database identifier for each of a number of objects stored in the database, appending the library identifier to each of the database identifiers to generate a unique reference identifier (DRef) for each of the plurality of objects stored in the database. Upon receiving an object request from an application, where the object request identifies one of the plurality of objects by its DRef, the method retrieves the object identified by the object request and stores the object identified by the object request in memory.

Abstract: Data clusters are added between functional blocks in a higher-level hierarchical circuit model. The data clusters account for inter-level parasitic values without flattening the circuit model to a lower hierarchical level and operate as an information graph or network between nodes, which can be used with the standard, or default, information graph between nodes. The data clusters also allow the use of standard functional blocks without introducing artificial nodes into the circuit at a lower level that could create a coupling point at a higher level. The use of data clusters allows rapid and accurate modeling of the circuit without flattening the circuit to the lowest level.

Abstract: A method for routing conductive paths in an integrated circuit, each conductive path having a first pin and a second pin is described herein. The method includes separating at least two conductive paths into groups based on the connection type of each of said conductive paths, the connection type for a given conductive path being determined based on the types of pins at each end of the conductive path, ranking each group based upon how constrained each connection type is relative to each other connection type, choosing the group having the most constrained connection type which has not yet been routed, and routing each conductive path within the group chosen during the choosing operation.

Abstract: A method for routing a conductive path in an integrated circuit is described. The method includes providing a side exiting bus comprising at least one pin, and providing a plurality of functional units, at least one functional unit having a pin required to be electrically connected to a pin in the side-exiting bus. The method further includes routing a first conductive path from one of the at least one pins in the side exiting bus to a point external to the functional units, the resulting conductive path spanning the width of the plurality of functional units, and routing a second conductive path in a straight line from the at least one pin in the at least one functional unit to a point on the first conductive path.