Patents by Inventor Pradyumna L. Prabhumirashi

Pradyumna L. Prabhumirashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10800939
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 13, 2020
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier
  • Patent number: 10676629
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: June 9, 2020
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier
  • Patent number: 10590294
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: March 17, 2020
    Assignees: NORTHWESTERN UNIVERSITY, PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier, Bok Y. Ahn, Jennifer A. Lewis
  • Publication number: 20180187032
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 5, 2018
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier, Bok Y. Ahn, Jennifer A. Lewis
  • Patent number: 9947724
    Abstract: A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: April 17, 2018
    Assignees: NORTHWESTERN UNIVERSITY, REGENTS OF THE UNIVERSITY OF MINNESOTA
    Inventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
  • Publication number: 20180094156
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 5, 2018
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier
  • Publication number: 20180086932
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier
  • Patent number: 9902866
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: February 27, 2018
    Assignees: Northwestern University, President and Fellows of Harvard College
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier, Bok Y. Ahn, Jennifer A. Lewis
  • Patent number: 9834693
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 5, 2017
    Assignee: Northwestern University
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier
  • Publication number: 20170162628
    Abstract: A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.
    Type: Application
    Filed: February 20, 2017
    Publication date: June 8, 2017
    Inventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
  • Patent number: 9613879
    Abstract: In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: April 4, 2017
    Assignees: NORTHWESTERN UNIVERSITY, REGENTS OF THE UNIVERITY OF MINNESOTA
    Inventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
  • Publication number: 20170081537
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Application
    Filed: August 24, 2015
    Publication date: March 23, 2017
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier, Bok Y. Ahn, Jennifer A. Lewis
  • Publication number: 20150102288
    Abstract: In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 16, 2015
    Inventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
  • Publication number: 20150072162
    Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.
    Type: Application
    Filed: July 30, 2014
    Publication date: March 12, 2015
    Inventors: Mark C. Hersam, Yu Teng Liang, Ethan B. Secor, Pradyumna L. Prabhumirashi, Kanan P. Puntambekar, Michael L. Geier