Patents by Inventor Pragyansri Pathi

Pragyansri Pathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10096474
    Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz, Sansaptak Dasgupta, Seung Hoon Sung, James M. Powers, Gilbert Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 9905693
    Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Pragyansri Pathi, Michael K. Harper
  • Publication number: 20170323965
    Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 9, 2017
    Inventors: Michael L. HATTENDORF, Pragyansri PATHI, Michael K. HARPER
  • Patent number: 9768249
    Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Pragyansri Pathi, Michael K. Harper
  • Publication number: 20170256408
    Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
    Type: Application
    Filed: May 24, 2017
    Publication date: September 7, 2017
    Inventors: Niloy MUKHERJEE, Niti GOEL, Sanaz K. GARDNER, Pragyansri PATHI, Matthew V. METZ, Sansaptak DASGUPTA, Seung Hoon SUNG, James M. POWERS, Gilbert DEWEY, Benjamin CHU-KUNG, Jack T. KAVALIEROS, Robert S. CHAU
  • Patent number: 9698013
    Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz, Sansaptak Dasgupta, Seung Hoon Sung, James M. Powers, Gilbert Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Publication number: 20170025499
    Abstract: Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.
    Type: Application
    Filed: October 6, 2016
    Publication date: January 26, 2017
    Inventors: Annalisa Cappellani, Pragyansri Pathi, Bruce E. Beattie, Abhijit Jayant Pethe
  • Patent number: 9472399
    Abstract: Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.
    Type: Grant
    Filed: May 24, 2015
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Pragyansri Pathi, Bruce E. Beattie, Abhijit Jayant Pethe
  • Publication number: 20160204193
    Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.
    Type: Application
    Filed: June 26, 2013
    Publication date: July 14, 2016
    Inventors: Michael L. HATTENDORF, Pragyansri PATHI, Michael K. HARPER
  • Publication number: 20160181099
    Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (I) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
    Type: Application
    Filed: September 4, 2013
    Publication date: June 23, 2016
    Inventors: Niloy MUKHERJEE, Niti GOEL, Sanaz K. GARDNER, Pragyansri PATHI, Matthew V. METZ, Sansaptak DASGUPTA, Seung Hoon SUNG, James M. POWERS, Gilbert DEWEY, Benjamin CHU-KUNG, Jack T. KAVALIEROS, Robert S. CHAU
  • Publication number: 20150255280
    Abstract: Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.
    Type: Application
    Filed: May 24, 2015
    Publication date: September 10, 2015
    Inventors: Annalisa Cappellani, Pragyansri Pathi, Bruce E. Beattie, Abhijit Jayant Pethe
  • Patent number: 9041106
    Abstract: Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Pragyansri Pathi, Bruce E. Beattie, Abhijit Jayant Pethe
  • Publication number: 20140084370
    Abstract: Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Annalisa Cappellani, Pragyansri Pathi, Bruce E. Beattie, Abhijit Jayant Pethe