Abstract: Several embodiments of a block downconverter using a SBAR bandpass filter in a superheterodyne receiver are disclosed. The block downconverter is coupled to receive a radio frequency input that includes a target region. The block downconverter is configured to produce a selected one of an overlapping plurality of portions of the target region as an intermediate frequency (IF) block having a fixed center frequency. Furthermore, the block downconverter includes a semiconductor bulk acoustic resonator (SBAR) filter that operates as an IF filter.

Abstract: An active state variable filter is presented including a summing circuit, a first and second integrator circuits, and an amplifier circuit. The summing circuit and first and second integrator circuits each include a programmable variable resistor for programmably varying the filtering characteristics of the state variable filter. Each programmable variable resistor receives a digital value and provides an electrical resistance corresponding to the digital value between a pair of terminals. Each programmable variable resistor may include multiple branch circuits extending between the pair of terminals, each branch circuit including an electrical resistor and an electrical switch connected in series. Alternately, each programmable variable resistor may include multiple subcircuits connected in series between the pair of terminals, each subcircuit including an electrical resistor and an electrical switch connected in parallel.

Abstract: A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.di-elect cons.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.di-elect cons. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.

Abstract: A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.epsilon.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.epsilon. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.

Abstract: A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer.

Abstract: An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.

Abstract: A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled.

Abstract: A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.

Abstract: A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer.

Abstract: A technique for utilizing an electric field to initiate electroless deposition of a material to form layers and/or structures on a semiconductor wafer. The wafer is disposed between a positive electrode and a negative electrode and disposed so that its deposition surface faces the positive electrode. A conductive surface on the wafer is then subjected to an electroless copper deposition solution. When copper is the conductive material being deposited, positive copper ions in the solution are repelled by the positive electrode and attracted by the negatively charged wafer surface. Once physical contact is made, the copper ions dissipate their charges by accepting electrons from the conductive surface, thereby forming copper atoms on the surface. The deposited copper have the catalytic properties so that when a reductant in the solution is absorbed at the copper sites and then oxidized, additional electrons are released into the conductive surface.

Abstract: An attenuated phase shifting mask has absorbers embedded (buried) in the mask substrate, instead of on the surface of the substrate. The buried absorbers allow for controlling attenuation and phase shifting parameters. The material composition and the thickness of the absorber regions determine the amount of attenuation that is to be achieved, as well as phase shifting in some instances. In other instances, offset distances of the absorbers from the surface of the mask control the phase shift. Light scattering and diffraction is reduced or eliminated by having the absorbers below the surface of the mask. By reducing light scattering and distortion, the mask of the present invention allows for PSM lithography techniques to be extended to ranges of shorter wavelength.

Abstract: A globally planarized binary optical mask has absorbers embedded (buried) in the mask substrate, instead of on the surface of the mask. Light scattering at rough vertical edges of absorbers of prior art masks are reduced or eliminated. Also, due to the buried nature of the absorbers, a triple singularity point encountered in prior art masks at the interface of three environments of quartz, absorber and air, no longer exists. The buried absorbers have an offset distance from the surface of the substrate so that with a minimum effective offset distance, defects and contaminants at the surface of the mask are no longer in the image plane, wherein alleviating a need for a pellicle to protect the mask surface. By reducing light scattering and distortion, the mask of the present invention allows for conventional optical lithography to be extended to ranges of shorter wavelength.

Abstract: A multi-layer PSM structure with multi-layer optical coating disposed between a quartz substrate and a surrounding medium, which typically is air. The multi-layer coating is comprised of a high index of refraction material overlying the quartz and a lower index of refraction material overlying the first. The multi-layer coating essentially functions as an anti-reflective coating to reduce scattering and reflection at the interface boundaries.

Abstract: A method of fabricating phase shifters with absorbing or attenuating sidewalls in order to inhibit or prevent light scattering at quartz-air interfaces. A quartz substrate is patterned and trenches are formed to provide "shifters". A metal film layer is formed along sidewalls of the trenches to provide the light absorbing characteristics. In one technique, the conformal metal layer is anisotropically etched while in another the metal layer is removed along with the photoresist by a lift-off technique.

Abstract: A phase shifting mask has phase shifters in which the sidewalls of the shifters are coated with a light absorbing or attenuating material. The light absorption at the sidewalls reduces the edges scattering and improves the resolution by obtaining similar transmission profiles from phase shifted and unshifted regions of the PSM.

Abstract: A submicron MOSFET is fabricated on an ultrathin layer with a generally intrinsic channel having a dopant concentration less than about 10.sup.16 cm.sup.-3. The channel thickness is preferably no greater than about 0.2 microns; the ratio of channel thickness to length is less than about 1:4, and preferably no greater than about 1:2. Punchthrough and other short-channel effects are inhibited by the application of an appropriate back-gate voltage, which may also be varied to adjust the voltage threshold.

Abstract: A lateral bipolar phototransistor having a floating, photosensitive base region is formed in a silicon layer on an insulator substrate. Insulated gate electrodes are formed above and below the base reigon and are voltage biased to create a field effect causing majority carriers to accumulate in the base region. The majority carriers accumulate in layers which face the respective gate electrodes and extend between an emitter and collector of the bipolar transistor. A bias voltage applied to the gate electrodes has a polarity opposite to a polarity of the majority carriers in the emitter and collector regions and is sufficiently high to bias field effect transistors constituted by the gate electrodes in combination with the emitter, base and collector of the bipolar phototransistor into cutoff. The accumulation creates a depleted base region with reduced parasitic capacitance and resistance, thereby enabling higher frequency operation and current gain.

Abstract: A self-aligned, lateral bipolar transistor is disclosed having at least one insulated metal gate for control of the base. The device has a Semiconductor-On-Insulator structure that reduces parasitic capacitances. Proper gate control provides a high and controllable gain of the device and also turns off the parasitic transistors. The device achieves variable, high gains as well as high frequencies due to the use of the gate. It requires no masking or doping manufacturing steps in addition to those used in making standard CMOS circuits, and is CMOS compatible. In a preferred embodiment, a second insulated metal back gate is used to further enhance the operation of the device.

Abstract: An LCLV is formed with a sapphire substrate base, a highly doped, thin silicon epitaxial layer forming an ohmic back contact on a smooth surface of the sapphire substrate, and a lightly doped, high resistivity silicon epitaxial layer in the range of about 20-60 microns thick on the back contact. The use of a sapphire substrate provides a better surface quality and higher resolution than previously available with the semiconductor substrates. Lattice defects in the thin back contact are reduced by the formation of a buried amorphous layer adjacent the sapphire substrate, and subsequent recrystallization thereof using the unamorphized portions of the back contact as recrystallization seeds. The application of the invention to both MOS and Schottky diode LCLVs is discussed.

Abstract: A method of fabricating CMOS circuit devices on an insulator substrate is disclosed in which a solid phase epitaxy process is applied to islands for the individual devices in the same step as the channel dopant implants. An ion species, preferably silicon for a silicon island, is implanted into each island at an energy and dosage sufficient to amorphize a buried layer of the island in the vicinity of an underlying insulated substrate; silicon-on-sapphire (SOS) is preferably employed. The buried layers are then recrystallized, using the unamorphized portions of the semiconducotr islands as crystallization seeds. Islands of generally uniform, high quality semiconductor material are thus obtained which utilize dopant implants more efficiently, and avoid prior parasitic transistors and leakage currents.