Patents by Inventor Prahladachar Jayaprakash Bharadwaj
Prahladachar Jayaprakash Bharadwaj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11726939Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: GrantFiled: September 25, 2021Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce Tennant, Mahesh Wagh
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Patent number: 11669481Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.Type: GrantFiled: December 22, 2021Date of Patent: June 6, 2023Assignee: Intel CorporationInventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
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Publication number: 20220114128Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
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Patent number: 11232058Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.Type: GrantFiled: August 29, 2019Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
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Publication number: 20220012203Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: ApplicationFiled: September 25, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
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Patent number: 11144492Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: GrantFiled: March 6, 2020Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
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Publication number: 20200210366Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: ApplicationFiled: March 6, 2020Publication date: July 2, 2020Applicant: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
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Patent number: 10691520Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.Type: GrantFiled: March 30, 2018Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Prahladachar Jayaprakash Bharadwaj, Alexander Brown, Debendra Das Sharma, Junaid Thaliyil
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Patent number: 10606785Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: GrantFiled: October 25, 2018Date of Patent: March 31, 2020Assignee: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
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Publication number: 20190384733Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
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Publication number: 20190065426Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: ApplicationFiled: October 25, 2018Publication date: February 28, 2019Applicant: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
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Publication number: 20180225167Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.Type: ApplicationFiled: March 30, 2018Publication date: August 9, 2018Applicant: Intel CorporationInventors: Prahladachar Jayaprakash Bharadwaj, Alexander Brown, Debendra Das Sharma, Junaid Thaliyil
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Patent number: 10019300Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.Type: GrantFiled: February 12, 2016Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Prahladachar Jayaprakash Bharadwaj, Alexander Brown, Debendra Das Sharma, Junaid Thaliyil
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Patent number: 9645965Abstract: A system and method comprising, in response to a first component and a link partner of the first component, undergoing equalization, the first component is to communicate a first set of data to the link partner component. The first component may comprise at least one receiver to receive a first set of equalization data. The first component may further comprise coefficient storage coupled to the receiver to store the equalization data. In addition, coefficient logic coupled to the coefficient storage to generate a first set of coefficients based on the first set of equalization data. The first component is to send the first set of coefficients to the link partner component.Type: GrantFiled: March 15, 2013Date of Patent: May 9, 2017Assignee: Intel CorporationInventors: Debendra Das Sharma, Kanaka Lakshimi Siva Prasad Gadey Naga Venkata, Prahladachar Jayaprakash Bharadwaj
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Publication number: 20160335148Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.Type: ApplicationFiled: February 12, 2016Publication date: November 17, 2016Applicant: Intel CorporationInventors: Prahladachar Jayaprakash Bharadwaj, Alexander Brown, Debendra Das Sharma, Junaid Thaliyil
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Patent number: 9454213Abstract: A method of staggering lanes in a peripheral component interconnect express (PCI-Express) port is described herein. The method includes initiating the port to enter or exit an electrical idle state. The method also includes forwarding a token to a predetermined lane of the port. Additionally, the method includes turning the predetermined lane ON or OFF by indication to an analog circuit interface. The method also includes forwarding the token to a neighboring lane when a staggering interval timer elapses.Type: GrantFiled: December 26, 2013Date of Patent: September 27, 2016Assignee: Intel CorporationInventors: Prahladachar Jayaprakash Bharadwaj, Debendra Das Sharma, Harshit Poladia, Kanaka Lakshmi Gadey Naga Venkata
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Patent number: 9262270Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.Type: GrantFiled: May 13, 2013Date of Patent: February 16, 2016Assignee: Intel CorporationInventors: Prahladachar Jayaprakash Bharadwaj, Alexander Brown, Debendra Das Sharma, Junaid Thaliyil
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Publication number: 20150185809Abstract: A method of staggering lanes in a peripheral component interconnect express (PCI-Express) port is described herein. The method includes initiating the port to enter or exit an electrical idle state. The method also includes forwarding a token to a predetermined lane of the port. Additionally, the method includes turning the predetermined lane ON or OFF by indication to an analog circuit interface. The method also includes forwarding the token to a neighboring lane when a staggering interval timer elapses.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Inventors: Prahladachar Jayaprakash Bharadwaj, Debendra Das Sharma, Harshit Poladia, Kanaka Lakshmi Gadey Naga Venkata
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Publication number: 20140281068Abstract: A system and method comprising, in response to a first component and a link partner of the first component, undergoing equalization, the first component is to communicate a first set of data to the link partner component. The first component may comprise at least one receiver to receive a first set of equalization data. The first component may further comprise coefficient storage coupled to the receiver to store the equalization data. In addition, coefficient logic coupled to the coefficient storage to generate a first set of coefficients based on the first set of equalization data. The first component is to send the first set of coefficients to the link partner component.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Debendra Das Sharma, Kanaka Lakshimi Siva Prasad Gadey Naga Venkata, Prahladachar Jayaprakash Bharadwaj
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Publication number: 20140189427Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.Type: ApplicationFiled: May 13, 2013Publication date: July 3, 2014Inventors: Prahladachar Jayaprakash Bharadwaj, Alexander Brown, Debendra Das Sharma, Junaid Thaliyil