Patents by Inventor Prajwal M. Kasturi

Prajwal M. Kasturi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Connectivity verification for flip-chip and advanced packaging technologies
    Patent number: 11639955
    Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: May 2, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Sanjay Sunder, Prajwal M. Kasturi, Joseph V. Pampanin, Craig S. Appel
  • CONNECTIVITY VERIFICATION FOR FLIP-CHIP AND ADVANCED PACKAGING TECHNOLOGIES
    Publication number: 20210382106
    Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Inventors: Sanjay SUNDER, Prajwal M. KASTURI, Joseph V. PAMPANIN, Craig S. APPEL
  • Connectivity verification for flip-chip and advanced packaging technologies
    Patent number: 11099229
    Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 24, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Sanjay Sunder, Prajwal M. Kasturi, Joseph V. Pampanin, Craig S. Appel
  • CONNECTIVITY VERIFICATION FOR FLIP-CHIP AND ADVANCED PACKAGING TECHNOLOGIES
    Publication number: 20210215754
    Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 15, 2021
    Applicants: Cisco Technology, Inc., Cisco Technology, Inc.
    Inventors: Sanjay Sunder, Prajwal M. Kasturi, Joseph V. Pampanin, Craig S. Appel