Abstract: Techniques for anomaly detection are described. An exemplary method includes receiving one or more requests to train an anomaly detection machine learning model using feedback-based training, the request to indicate one or more of a type of analysis to perform, a model selection indication, and a configuration for a training dataset; training the anomaly detection machine learning model according to the one or more requests using the training data; performing feedback-based training on the trained anomaly detection machine learning model; and using the retrained anomaly detection machine learning model.

Abstract: An image processing system, includes an image sensor, a bus structure coupled to the image sensor, and a system memory coupled to the image sensor via the bus structure. A direct memory access (DMA) controller is coupled to the bus structure. The DMA controller includes in-line logic hardware configured to retrieve raw pixel data from the image sensor, and internally process the retrieved raw pixel data thereby providing processed pixel data.

Abstract: A memory device can include a plurality of memory cells for storing data, a memory interface configured to store and retrieve data at the plurality of memory cells, a logic unit comprising digital circuitry configured to perform mathematic and logic operations, and a control circuitry configured to control operation of the memory device.

Abstract: A memory device can include a plurality of memory cells for storing data, a memory interface configured to store and retrieve data at the plurality of memory cells, a logic unit comprising digital circuitry configured to perform mathematic and logic operations, and a control circuitry configured to control operation of the memory device.

Abstract: Single Program, Multiple Data (SPMD) parallel processing of SPMD instructions can be generated among processors assigned to a task in a plurality of threads. The SPMD parallel processing can be increased in speed by performing predicated looping with the SPMD instructions in an activated SPMD mode of operation over a non-SPMD mode. Execution of overhead instructions is removed from the SPMD instructions associated with a thread in order to only execute the loop body of a loop associated with a data element of a data set in an enhanced Zero Loop Overhead (ZOL) device.

Abstract: Single Program, Multiple Data (SPMD) parallel processing of SPMD instructions can be generated among processors assigned to a task in a plurality of threads. The SPMD parallel processing can be increased in speed by performing predicated looping with the SPMD instructions in an activated SPMD mode of operation over a non-SPMD mode. Execution of overhead instructions is removed from the SPMD instructions associated with a thread in order to only execute the loop body of a loop associated with a data element of a data set in an enhanced Zero Loop Overhead (ZOL) device.

Abstract: Architecture includes an integrated tool that allows a tester to automatically persist test plan information in association with related content while the tester is interacting with that content in an IDE. The tool further enables the tester to formally associate actions/expectations with specific items of content. In previous solutions, references to existing content are often lost due to inexact or missing descriptions. Formal associations allow for reuse of valuable content and avoid unnecessary recreation. The tool is integrated with the IDE, and thus, does not necessitate that the tester manually type or write descriptions of intent and expectations. This reduces the test plan cost significantly. The tool also persists information in a formal, self-describing format that enables easy consumption by either human testers or secondary software applications (e.g., for the purposes of identifying plans, performing associated actions and verifying expected behavior).