Abstract: Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.

Abstract: A system for accessing memory is disclosed. The system comprises a first communication interface configured to receive from an external processor a request for data. The system further comprises a second communication interface configured to communicate with an external memory module to provide the external processor indirect access to the data stored on the external memory module. The system further comprises a memory-side cache configured to cache the data obtained from the external memory module. The cache comprises a plurality of cache entries. The data obtained from the external memory is cached in one of the cache entries, and wherein the one of the cache entries comprises a plurality of cache data sectors with corresponding individual cache data sector valid status indicators and corresponding individual cache data sector modified status indicators and a common tag field for the plurality of cache data sectors.

Abstract: Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.

Abstract: A computer system and a method for allocating power to hot-plugged adapter cards placed in a card slot so as to delay, the power allocation until a user is clear of the adapter card. The computer system conventionally includes a processor, a card slot in data communication with the processor, a memory in data communication with the processor, and a power supply in electrical communication with the processor. The memory stores computer-readable data that includes code to be operated on by the processor to allocate power to the card slot upon both a detection of a change of state of the card slot and the occurrence of a predefined system event. The predefined system event is typically a system interrupt that is generated in response to an activation of a switch in electrical communication with the processor.