Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to identify one or more display segments of a display panel, each display segment associated with one of a plurality of lanes of a main link coupled with the interface, independently control enabling and disabling of the display segments and associated lanes, and communicate information on each of the lanes of the main link associated with enabled display segments, and to withhold communicating information on each of the lanes of the main link associated disabled display segments.

Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.

Abstract: Micro LEDs may be placed on a substrate in regularly spaced rows with an empty row between at least two successive rows of micro LED. A micro solar cell may then be placed in the empty row.

Abstract: Micro LEDs may be placed on a substrate in regularly spaced rows with an empty row between at least two successive rows of micro LED. A micro solar cell may then be placed in the empty row.

Abstract: A distributed memory panel including a panel, a light emitter of a pixel on the panel, and integrated circuit on the panel. The integrated circuit to include a memory wherein the memory is exclusively associated with the light emitter and a driver to drive the light emitter of the pixel.

Abstract: In an embodiment, processor includes at least one logic circuit to generate information to be output from the processor; an input/output (IO) interface circuit coupled to the at least one logic circuit to receive and transmit the information; a voltage regulator to provide an operating voltage to the IO interface circuit; and a controller to control the voltage regulator to provide the operating voltage at an adjusted level from a nominal operating voltage based on a process variation of at least a portion of a die including the IO interface circuit. Other embodiments are described and claimed.

Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.

Abstract: By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.

Abstract: An adaptive impedance matching arrangement has an adaptive impedance circuit and a control circuit. The adaptive impedance circuit matches the impedance of a bus and is controlled according to control bits supplied by the control circuit. The control bits are updated according to a signal indicating the state of a queue maintaining transactions for the bus.