Patents by Inventor Prakash Makwana

Prakash Makwana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations
    Patent number: 8355294
    Abstract: A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: January 15, 2013
    Assignee: Freescale Semiconductor, Inc
    Inventors: Prakash Makwana, Prabhjot Singh
  • SYNCHRONOUS DATA PROCESSING SYSTEM AND METHOD
    Publication number: 20120239961
    Abstract: A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 20, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Prakash Makwana, Prabhjot Singh