Abstract: Integrated circuit failures caused by metastability related to assertion of asynchronous resets frequently escape detection before fabrication, causing design respins and severe economic loss. The numerous reset signals, flip-flops and complex logical interactions inherent in an integrated circuit cause an analysis for reset-metastability failures to be extremely noisy, reporting an unmanageable number of false failures and making early removal of failures impractical. Said noisy reporting arises because many flip-flops where reset-metastability manifests do not necessarily cause overall failure. An effective analysis of reset-metastability failures must identify all potential failures, but also must only report true failure potential. The present invention maximizes noise reduction by applying special conditions to identify flip-flops manifesting reset-metastability without causing integrated circuit failure, which can thereby be deemed safe.

Abstract: Methods and systems are described to identify potential failures caused by metastability arising from signal propagation between asynchronous clock domains in integrated circuits with multiple operating modes, each mode allowing selected clocks to propagate. Typical integrated circuits have numerous operating modes, and hence numerous possible clock combinations, each combination causing different asynchronous clock-domain crossings, and hence different potential failures. Since verification for even one clock combination is time-consuming, explicitly enumerating and verifying all possible clock combinations is unviable. In practice very few clock combinations are verified, possibly missing failures.

Abstract: A plasma based deposition process to deposit thin film on the inner surfaces of the shaped objects such as plastic or metallic object like bottles, hollow tubes etc. at room temperature has been developed. In present invention uniform hydrogenated amorphous carbon (also called Diamond-Like Carbon, DLC) films on inner surfaces of plastic bottles is successfully deposited. Applications of such product include entire food and drug industries. There is a huge demand of polyethylene terephthalate (PET) or polyethylene naphthalate (PEN)) bottles, meant for the storage of potable water, carbonated soft drinks, wines, medicines etc. However, the higher cost prohibits their wide, spread use. The cheaper alternative is to use plastic bottles inside coated with chemically inert material such as Diamond-Like Carbon (DLC) will be commercially viable. Inventor process can be scaled up for mass production.

Abstract: A process for the preparation of nano structured silicon thin film using radio frequency (rf) plasma discharge useful for light emitting devices such as light emitting diode, laser etc. which allows precise control of the nanocrystal size of silicon and its uniform distribution without doping using a plasma processing for obtaining efficient photoluminescence at room temperature.

Abstract: A plasma based deposition process to deposit thin film on the inner surfaces of the shaped objects such as plastic or metallic object like bottles, hollow tubes etc. at room temperature has been developed. In present invention uniform hydrogenated amorphous carbon (also called Diamond-Like Carbon, DLC) films on inner surfaces of plastic bottles is successfully deposited. Applications of such product include entire food and drug industries. There is a huge demand of polyethylene terephthalate (PET) or polyethylene naphthalate (PEN)) bottles, meant for the storage of potable water, carbonated soft drinks, wines, medicines etc. However, the higher cost prohibits their wide, spread use. The cheaper alternative is to use plastic bottles inside coated with chemically inert material such as Diamond-Like Carbon (DLC) will be commercially viable. Inventor process can be scaled up for mass production.

Abstract: The present invention provides a process for the preparation of nano structured silicon thin film using radio frequency (rf) plasma discharge useful for light emitting devices such as light emitting diode, laser etc. The present invention shows the possibility of precise control of the nanocrystal size of silicon and its uniform distribution without doping using plasma processing for obtaining efficient photoluminescence at room temperature. Process developed to deposit the photo luminescent nano structured silicon thin films using plasma enhanced chemical vapour deposition technique can find use in electroluminescence devices like light emitting diodes (LEDs), LASER etc. This could also be advantageous for integration of silicon photonic devices with the existing silicon microelectronic technology.

Abstract: A method and apparatus are described that facilitate validation of a hardware design having multiple hierarchical levels. In one embodiment, a representation of the hardware design is received, and the hardware design is validated by performing validation processing on a plurality of sub-problems. Each of the plurality of sub-problems covers a computationally feasible size of the hardware design at a corresponding hierarchical level. In another embodiment, validation of a hardware design includes making use of validation processing previously performed with respect to one or more modules included in the hardware design based on the hierarchical relationship between these modules and other modules included in the hardware design.

Abstract: Method and apparatus are provided for facilitating analysis of the intended behavior of a hardware design. According to one embodiment of the present invention, a language-based representation of a hardware design is received. Multiple design verification checks are generated for use in connection with model checking by applying a set of one or more predetermined properties to the language-based representation of the hardware design. Then, the hardware design, as implemented according to the language-based representation, is verified against intended behavior, represented by the set of one or more predetermined properties, by determining whether one or more of the design verification checks are violated by the hardware design. Finally, results of the verification may be reported.

Abstract: A method and apparatus for characterizing information about design attributes is described. The characterization process may begin with determining the dependency among the attributes within a hardware design. Once the dependency is determined, the most relevant information about the hardware design attribute may be highlighted. A user can then focus their attention on the highlighted aspects of the design attribute to draw conclusions about the hardware design as a whole.

Abstract: A method and apparatus for characterizing information about design attributes is described. The characterization process may begin with determining the dependency among the attributes within a hardware design. Once the dependency is determined, the most relevant information about the hardware design attribute may be highlighted. A user can then focus their attention on the highlighted aspects of the design attribute to draw conclusions about the hardware design as a whole.

Abstract: A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, hardware design defects can be detected using a novel Intent-Driven Verification process. First, a representation of a hardware design and information regarding the intended flow of logical signals among variables in the representation are received. Then, the existence of potential errors in the hardware design may be inferred based upon the information regarding the intended flow of logical signals by (1) translating the information regarding the intended flow of logical signals into a comprehensive set of checks that must hold true in order for the hardware design to operate in accordance with the intended flow of logical signals, and (2) determining if any of the checks can be violated during operation of circuitry represented by the hardware design.

Abstract: A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, multiple design verification checks associated with a hardware design are linked by determining dependency reationships among the multiple design verification checks. Each of the design verification checks represent a condition that must hold true in order for the hardware design to operate in accordance with an intended flow of logical signals in the hardware design.

Abstract: A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a comprehensive set of design verification checks may be formulated by applying predetermined properties to an annotated hardware design representation. Information regarding the intended flow of logical signals in the hardware design is received by way of annotations in a control file or annotations embedded in the hardware design representation itself. The annotations include (1) an indication of one or more variables in the representation of the hardware design through which the logical signals pass, and (2) an indication of one or more conditions under which each of the one or more variables are to be associated with each of a set of states. Checks are then automatically formulated based upon a predetermined set of properties that must hold true in order for the hardware design to operate in accordance with the intended flow.

Abstract: A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a method is provided for explicitly associating state information with variables of a language description of a hardware design. Information regarding the intended flow of logical signals among the variables, which represent interconnects in the hardware design through with the logical signals pass, is received. Then, the intended flow of logical signals is modeled by associating state information with the variables in accordance with the intended flow of logical signals. Advantageously, in this manner, the integrity of the data flow can be verified by confirming checks that are expressed as a function of the states associated with the variables.

Abstract: A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.

Abstract: A method and structure for testing a circuit with reduced test pattern generation constraints. The circuit includes a first logic circuit coupled to receive input signals from a first flip-flop and a second flip-flop. The first and second flip-flops store part of a test pattern generated to test the circuit. The circuit also includes first and second three state driver (TSD) circuits coupled to receive output signals from the first logic circuit. The output leads of the first and second TSDs are connected to a single input lead of a second logic circuit. The first and second TSDs receive control signals that enable and disable the first and second TSDs. The control signals are provided by the first logic circuit or, alternatively, by a separate decoder. During test operations, the control signals enable the first and second TSDs substantially simultaneously for a predetermined duration.