Patents by Inventor Prakash Narayanan
Prakash Narayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180045778Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: ApplicationFiled: October 2, 2017Publication date: February 15, 2018Inventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Patent number: 9823282Abstract: An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; and an electronic monitoring circuit (100) that has a variably operable reference circuit (150) responsive to an input register (155) and having an output, comparison circuitry (110) having plural outputs and having a first input coupled to the output of said variably operable reference circuit (150) and a set of second inputs each second input coupled to a respective one of said power grid points (30.i); and an output register (120) having at least two register bit cells (120.i) respectively fed by the plural outputs of said comparison circuitry (110.i). Other integrated circuits, and processes of testing and of manufacturing are also disclosed.Type: GrantFiled: June 10, 2015Date of Patent: November 21, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Sudhir Polarouthu
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Publication number: 20170315174Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Patent number: 9791505Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: GrantFiled: April 29, 2016Date of Patent: October 17, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Publication number: 20170157524Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
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Publication number: 20170125125Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit of the system-on-a-chip (SoC) type. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: ApplicationFiled: March 10, 2016Publication date: May 4, 2017Inventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
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Publication number: 20160069958Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.Type: ApplicationFiled: November 18, 2015Publication date: March 10, 2016Inventors: Prakash Narayanan, Rubin A. Parekhji, Arvind Jain, Sundarrajan Subramanian
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Publication number: 20160003900Abstract: Circuits and methods for performing self-test of digital circuits are disclosed. In an embodiment, a method includes applying a set of test patterns for performing scan testing of a digital circuit to generate scan outputs from the digital circuit. The set of test patterns includes one or more sets of base test patterns already stored in a memory and one or more sets of derived test patterns temporarily generated from the one or more sets of base test patterns. The method further includes comparing the scan outputs received from the digital circuit with reference scan outputs corresponding to the digital circuit for fault detection in the digital circuit to thereby achieve a target fault coverage of the scan testing of the digital circuit. The reference scan outputs corresponding to the digital circuit are stored in the memory.Type: ApplicationFiled: March 4, 2015Publication date: January 7, 2016Inventors: Prakash Narayanan, Rubin Ajit Parekhji
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Patent number: 9229055Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.Type: GrantFiled: June 18, 2015Date of Patent: January 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji
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Publication number: 20150285860Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji
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Publication number: 20150276824Abstract: An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; and an electronic monitoring circuit (100) that has a variably operable reference circuit (150) responsive to an input register (155) and having an output, comparison circuitry (110) having plural outputs and having a first input coupled to the output of said variably operable reference circuit (150) and a set of second inputs each second input coupled to a respective one of said power grid points (30.i); and an output register (120) having at least two register bit cells (120.i) respectively fed by the plural outputs of said comparison circuitry (110.i). Other integrated circuits, and processes of testing and of manufacturing are also disclosed.Type: ApplicationFiled: June 10, 2015Publication date: October 1, 2015Inventors: Prakash Narayanan, Sudhir Polarouthu
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Patent number: 9091729Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.Type: GrantFiled: September 16, 2014Date of Patent: July 28, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji
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Patent number: 9081063Abstract: An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; and an electronic monitoring circuit (100) that has a variably operable reference circuit (150) responsive to an input register (155) and having an output, comparison circuitry (110) having plural outputs and having a first input coupled to the output of said variably operable reference circuit (150) and a set of second inputs each second input coupled to a respective one of said power grid points (30.i); and an output register (120) having at least two register bit cells (120.i) respectively fed by the plural outputs of said comparison circuitry (110.i). Other integrated circuits, and processes of testing and of manufacturing are also disclosed.Type: GrantFiled: March 29, 2011Date of Patent: July 14, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Sudhir Polarouthu
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Patent number: 9053273Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.Type: GrantFiled: July 20, 2012Date of Patent: June 9, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sumanth Reddy Poddutur, Prakash Narayanan, Vivek Singhal
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Patent number: 8972807Abstract: Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern.Type: GrantFiled: May 14, 2012Date of Patent: March 3, 2015Assignee: Texas Instruments IncorporatedInventors: Rajesh Mittal, Puneet Sabbarwal, Prakash Narayanan, Rubin Ajit Parekhji
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Publication number: 20150006987Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Applicant: Texas Instruments IncorporatedInventors: Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji
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Patent number: 8887018Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.Type: GrantFiled: October 14, 2010Date of Patent: November 11, 2014Assignee: Texas Instruments IncorporatedInventors: Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji
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Patent number: 8839063Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.Type: GrantFiled: January 24, 2013Date of Patent: September 16, 2014Assignee: Texas Instruments IncorporatedInventors: Rubin Ajit Parekhji, Srivaths Ravi, Prakash Narayanan, Milan Shetty
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Publication number: 20140208177Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.Type: ApplicationFiled: January 24, 2013Publication date: July 24, 2014Applicant: Texas Instruments IncorporatedInventors: Rubin Ajit Parekhji, Srivaths Ravi, Prakash Narayanan, Milan Shetty
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Publication number: 20140021993Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: Texas Instruments IncorporatedInventors: SUMANTH REDDY PODDUTUR, Prakash Narayanan, Vivek Singhal