Patents by Inventor Prakash Parikh

Prakash Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060271399
    Abstract: A computer-based system and method for supporting office/practice management offers enhanced patient/client/customer registration functionalities that facilitate efficient and reliable intake and maintenance of patient/client/customer relationships. The system/method includes a patient preference functionality that facilitates appointment scheduling and a “patient flag” functionality that supports extensibility (e.g., linking to an associated document, record or other electronically accessible resource).
    Type: Application
    Filed: May 31, 2005
    Publication date: November 30, 2006
    Inventors: James Robson, Jason Epperson, Joseph Acker, Michael Brooks, Michael Swyers, Prakash Parikh
  • Patent number: 6845341
    Abstract: A method and mechanism for performing improved performance analysis upon transaction level models. A system block may be modeled using transaction model at different levels of abstraction. A testbench may be used to apply a set of stimuli to a transaction model (e.g. a TLM model) and a RTL equivalent model, and store the resulting timing information into a database. The timing information stored in the database may be used to validate the performance of the transaction models and system block. The testbench may analyze transaction models in the TLM domain and the RTL domain through the employment of TVM (transaction verification models) which are components that maps the transaction-level requests made by a test stimulus generator to a detailed signal-level protocol on the RTL design.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: January 18, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Aaron Beverly, Franco Carbognani, Shampa Gupta, Prakash Parikh
  • Publication number: 20040054500
    Abstract: A method and mechanism for performing improved performance analysis upon transaction level models. A system block may be modeled using transaction model at different levels of abstraction. A testbench may be used to apply a set of stimuli to a transaction model (e.g. a TLM model) and a RTL equivalent model, and store the resulting timing information into a database. The timing information stored in the database may be used to validate the performance of the transaction models and system block. The testbench may analyze transaction models in the TLM domain and the RTL domain through the employment of TVM (transaction verification models) which are components that maps the transaction-level requests made by a test stimulus generator to a detailed signal-level protocol on the RTL design.
    Type: Application
    Filed: March 24, 2003
    Publication date: March 18, 2004
    Applicant: CADENCE DESIGNS SYSTEMS
    Inventors: Aaron Beverly, Franco Carbognani, Shampa Gupta, Prakash Parikh
  • Patent number: 4264360
    Abstract: A copper base alloy and process of treating same. The alloy consists essentially of: about 1.0 to 4.5% silicon; about 1.0 to 5.0% tin; about 0.01 to 0.45% chromium; and the balance essentially copper. Preferably, the chromium level is less than about 0.12% in order to provide good tool wear characteristics.
    Type: Grant
    Filed: October 9, 1979
    Date of Patent: April 28, 1981
    Assignee: Olin Corporation
    Inventors: Prakash Parikh, Eugene Shapiro