Patents by Inventor Prakash Pillai

Prakash Pillai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12253966
    Abstract: A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power rail. A signal indicative of the state of the device is encoded for transmission to the host processor of the host system. PCIe link training is performed via a PCIe interface with the host system. The PCIe link training is initiated based on the signal indicative of the state of the device.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 18, 2025
    Assignee: Intel Corporation
    Inventors: Prakash Pillai, Sagar Pawar, Raghavendra Nagaraj, Ovais Pir, Pannerkumar Rajagopal
  • Patent number: 12007823
    Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Pannerkumar Rajagopal, Raghavendra N, Ovais Pir, Prakash Pillai, Sagar C. Pawar
  • Publication number: 20240111560
    Abstract: Embodiments herein relate to providing uniform servicing of workloads at a set of servers in a computer network. A platform determines and meets the performance requirements of a workload by scaling a performance capability of a group of processing units such as central processing units (CPUs) which are assigned to service the workload. This can involve increasing the power (P) state of one or more of the processing units to a highest P state in the group, so that every processing units in the group provides the same performance for a given workload. The platform can manage scaling of the processing units performance by reading a performance profile list which indicates minimum and maximum scaling points for programs that are executed to service the workload.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Subhankar Panda, Rupal M. Parikh, Gaurav Porwal, Raghavendra Nagaraj, Sagar C. Pawar, Prakash Pillai
  • Publication number: 20240004454
    Abstract: In an embodiment, a processor may include processing circuits to execute instructions. The processor may also include at least one circuit to: detect a management mode trigger event during operation of the processor in a first power state, the management mode trigger event to initiate a management mode in the processor; in response to a detection of the management mode trigger event, switch the processor from the first power state to a second power state; and after a switch of the processor from the first power state to the second power state, initiate the management mode in the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Sagar C. Pawar, Pannerkumar Rajagopal, Raghavendra Nagaraj, Ovais F. Pir, Prakash Pillai
  • Patent number: 11720401
    Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Pannerkumar Rajagopal, Murali R Iyengar, Karunakara Kotary, Ovais Pir, Sagar C Pawar, Prakash Pillai, Raghavendra N, Aneesh A Tuljapurkar
  • Publication number: 20230086027
    Abstract: A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power rail. A signal indicative of the state of the device is encoded for transmission to the host processor of the host system. PCIe link training is performed via a PCIe interface with the host system. The PCIe link training is initiated based on the signal indicative of the state of the device.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Prakash Pillai, Sagar Pawar, Raghavendra Nagaraj, Ovais Pir, Pannerkumar Rajagopal
  • Publication number: 20220391003
    Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.
    Type: Application
    Filed: March 23, 2022
    Publication date: December 8, 2022
    Inventors: Pannerkumar Rajagopal, Raghavendra N, Ovais Pir, Prakash Pillai, Sagar C. Pawar
  • Patent number: 11432421
    Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Samarth Alva, Krishnakumar Varadarajan, Yogesh Channaiah, Prakash Pillai, Sagar Pawar, Aneesh Tuljapurkar, Raghavendra N
  • Publication number: 20220206591
    Abstract: Methods and apparatus for adaptive keyboard scanning are disclosed. A disclosed example apparatus to adaptively control operation of a keyboard includes at least one memory, instructions, and processor circuitry. The processor circuitry is to determine whether to operate the keyboard in a first mode or in a second mode different from the first mode, the first mode corresponding to a first number of keys, the second mode corresponding to a second number of keys less than the first number of keys, and set the keyboard to operate in the first mode or the second mode based on the determination.
    Type: Application
    Filed: March 18, 2022
    Publication date: June 30, 2022
    Inventors: Sagar Pawar, Raghavendra Nagaraj, Prakash Pillai, Ovais Pir, Pannerkumar Rajagopal
  • Publication number: 20220198022
    Abstract: A power-up scheme for a computing system that applies a biometric sensor (e.g., a fingerprint sensor, eye sensor, etc.) to authenticate a user before enabling power-up of the computing system or to resume transition to a power state (e.g., one of the power states defined by the Advance Configuration and Power Interface (ACPI)). Output of the biometric sensor is compared against data of a registered user for a match. The data may include an original copy of an output of the biometric sensor saved in a non-volatile memory (e.g., serial peripheral interface (SPI) flash device). If a match exists, a logic in the computing system will allow the computing system to power-up. In the absence of a match, the computing system will not be powered up. In some examples, battery charging is also disabled if the match is not found.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Sagar C. Pawar, Pannerkumar Rajagopal, Raghavendra N, Prakash Pillai, Ovais Pir
  • Publication number: 20210373833
    Abstract: Techniques and mechanisms for power management of display devices based on an indication that a user exhibits interest in one, but not all, of said display devices. In an embodiment, logic of a computer device identifies a condition wherein a user of the computer device exhibits insufficient interest in a first display device, while exhibiting at least some interest user in a second display device. The first display device and the second display device support an extended display mode of an operating system. Based on the condition, the logic automatically reduces a consumption of power by the first display device. Of the first display device and the second display device, only the first display device is subjected to a power state transition based on the condition.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 2, 2021
    Applicant: Intel Corporation
    Inventors: Sagar Pawar, Prakash Pillai, Ovais Pir, Murali Iyengar, Pannerkumar Rajagopal, Raghavendra N, Aneesh Tuljapurkar
  • Patent number: 10747779
    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Sagar C. Pawar, Prakash Pillai, Raghavendra N, Aneesh A. Tuljapurkar
  • Publication number: 20200245483
    Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Samarth Alva, Krishnakumar Varadarajan, Yogesh Channaiah, Prakash Pillai, Sagar Pawar, Aneesh Tuljapurkar, Raghavendra N.
  • Publication number: 20200225994
    Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Pannerkumar Rajagopal, Murali R. Iyengar, Karunakara Kotary, Ovais Pir, Sagar C. Pawar, Prakash Pillai, Raghavendra N., Aneesh A. Tuljapurkar
  • Patent number: 10653026
    Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Samarth Alva, Krishnakumar Varadarajan, Yogesh Channaiah, Prakash Pillai, Sagar Pawar, Aneesh Tuljapurkar, Raghavendra N
  • Publication number: 20200125579
    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overlocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting.
    Type: Application
    Filed: May 30, 2019
    Publication date: April 23, 2020
    Inventors: Sagar C. Pawar, Prakash Pillai, Raghavendra N, Aneesh A. Tuljapurkar
  • Patent number: 10516285
    Abstract: Techniques for wireless charging in a system, method, and apparatus are described herein. An apparatus for charging at a wireless power receiver may include logic. The logic is configured to supply voltage received at the wireless power receiver at a first power level to a battery that is initially fully discharged, wherein the power of the first power level is received during a predefined interval of a fully discharged battery protocol. The logic is to monitor a second power level available at the battery, and initiate a wireless handshake with a wireless power transmitter inductively coupled to the wireless power receiver indicating configurations of the wireless power receiver upon detection of the second power level meeting or exceeding a predefined threshold.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Sagar C. Pawar, Prakash Pillai
  • Publication number: 20190215975
    Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 11, 2019
    Inventors: Samarth Alva, Krishnakumar Varadarajan, Yogesh Channaiah, Prakash Pillai, Sagar Pawar, Aneesh Tuljapurkar, Raghavendra N
  • Patent number: 10318547
    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Sagar C. Pawar, Prakash Pillai, Raghavendra N, Aneesh A. Tuljapurkar
  • Publication number: 20180293291
    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: Sagar C. Pawar, Prakash Pillai, Raghavendra N, Aneesh A. Tuljapurkar