Patents by Inventor Prakash Rau Mokhna Rau

Prakash Rau Mokhna Rau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210043644
    Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.
    Type: Application
    Filed: August 5, 2019
    Publication date: February 11, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Yi Hu, Merri L. Carlson, Anilkumar Chandolu, Indra V. Chary, David Daycock, Harsh Narendrakumar Jain, Matthew J. King, Jian Li, Brett D. Lowe, Prakash Rau Mokhna Rau, Lifang Xu
  • Publication number: 20210013221
    Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 14, 2021
    Applicant: Micron Technology, Inc.
    Inventors: David Daycock, Prakash Rau Mokhna Rau
  • Patent number: 10586801
    Abstract: 3D NAND memory cells can include a source layer, a dielectric layer disposed on the source layer, and a select gate source (SGS) layer disposed on the dielectric layer. A plurality of alternating layers of conducting material and insulating material can be disposed on the SGS layer. A conductive channel can be formed within a cell pillar trench. The conductive channel can be in contact with the source layer and the plurality of alternating layers. The cell pillar trench can be positioned in a substantially perpendicular orientation with respect to the plurality of alternating layers.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Prakash Rau Mokhna Rau, Wesly McKinsey, Rithu Bhonsle
  • Publication number: 20190294330
    Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Applicant: Intel Corporation
    Inventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
  • Patent number: 10318170
    Abstract: Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
  • Patent number: 10304749
    Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Christopher W. Petz, Philip M. Campbell, Wei Yeeng Ng, Kunal Bhaskar Shrotri, Saurabh Keshav, John Mark Meldrim, Prakash Rau Mokhna Rau, Tom Jibu John
  • Publication number: 20190043871
    Abstract: 3D NAND memory cells can include a source layer, a dielectric layer disposed on the source layer, and a select gate source (SGS) layer disposed on the dielectric layer. A plurality of alternating layers of conducting material and insulating material can be disposed on the SGS layer. A conductive channel can be formed within a cell pillar trench. The conductive channel can be in contact with the source layer and the plurality of alternating layers. The cell pillar trench can be positioned in a substantially perpendicular orientation with respect to the plurality of alternating layers.
    Type: Application
    Filed: January 12, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Prakash Rau Mokhna Rau, Wesly McKinsey, Rithu Bhonsle
  • Publication number: 20180366386
    Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Applicant: Intel Corporation
    Inventors: Christopher W. Petz, Philip M. Campbell, Wei Yeeng Ng, Kunal Bhaskar Shrotri, Saurabh Keshav, John Mark Meldrim, Prakash Rau Mokhna Rau, Tom Jibu John
  • Publication number: 20180307412
    Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.
    Type: Application
    Filed: January 2, 2018
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
  • Patent number: 9857989
    Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can also include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods can include or otherwise utilize such solid state memory components.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau