Abstract: Improved parasitic analysis of a design of an electrical circuit (e.g. a PCB coupled to an IC package) can use a first parasitic analysis to identify a first set of pins having excessive parasitic values (“hotspots” in the design) and then identify a second set of pins that do not have excessive parasitic values. The pins in the second set can be clustered (e.g. using a grid of cells) to reduce a model size for calculations in a second parasitic analysis, and the pins in the first set can be analyzed in the second parasitic analysis either individually or in clusters of similar pins with excessive parasitic values.

Abstract: Systems and methods are provided for performing a simulation of an integrated circuit, integrated circuit package, or printed circuit board design. A representation of the design is accessed that includes a plurality of components inside a volume. The volume is discretized into a plurality of volumetric elements. A removable signal transmission element is identified in the volume. The signal transmission element is removed from the volume. An electrical parameter associated with the removed signal transmission element is identified. A finite element method operation is performed to identify a characteristic of the design based on the discretized volume having the signal transmission element removed and the electrical parameter, an electrical impact of the signal transmission element on the package being retained based on the electrical parameter.