Abstract: A duty cycle correction circuit includes a duty cycle adjuster that is configured to receive first and second differential input signals having first and second duty cycles, respectively, that are distorted with respect to a reference duty cycle. The duty cycle adjuster is further configured to iteratively adjust the first and second duty cycles to generate first and second differential output signals having third and fourth duty cycles that are within a predefined range of the reference duty cycle, respectively. During each iteration, the duty cycle adjuster adjusts the first and second duty cycles based on correction bits that are generated based on a duty cycle detection signal that indicates whether the third duty cycle is greater than or less than the fourth duty cycle, and a lock signal that is activated when the duty cycle detection signal toggles from one logic state to another.