Patents by Inventor Pramit SARKAR

Pramit SARKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250055451
    Abstract: A GaN based under voltage lock-out circuit includes a supply voltage input, a signal output, and a reference voltage circuit interface. Also included is a first transistor having a source and gate both coupled to the supply voltage input, and a drain coupled to a first port of the reference voltage circuit interface. Further included is a second transistor having a gate coupled to the drain of the first transistor via a second port of the reference voltage circuit interface, a drain coupled to the signal output and coupled, via a first resistor, to the supply voltage input, and a source coupled, via a second resistor, to a ground potential. Also included is a third transistor having a gate coupled to the signal output, a drain coupled through a third resistor to the source of the first transistor, and a third source coupled to the drain of the second transistor.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Pramit SARKAR, Manish SHAH
  • Patent number: 12132470
    Abstract: An integrated circuit includes a substrate, a GaN FET power switch disposed on the substrate, and a totally-GaN-based driver disposed on the substrate and coupled to the GaN FET power switch. The totally-GaN-based driver has an input terminal for receiving a supply voltage and includes an under-voltage detector having an output terminal. The under-voltage detector outputs a UVLO signal when the supply voltage is below a low-to-high threshold value, and does not output the UVLO signal when the supply voltage is above the low-to-high threshold value. The totally-GaN-based driver includes a pulse stretcher having an input terminal coupled to the output terminal of the under-voltage detector, and an output terminal for outputting a stretched_UVLO signal for a predetermined amount of time after the supply voltage first rises above the low-to-high threshold value.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: October 29, 2024
    Assignee: TAGORE TECHNOLOGY, INC.
    Inventors: Pramit Sarkar, Manish Shah
  • Publication number: 20230188128
    Abstract: An integrated circuit includes a substrate, a GaN FET power switch disposed on the substrate, and a totally-GaN-based driver disposed on the substrate and coupled to the GaN FET power switch. The totally-GaN-based driver has an input terminal for receiving a supply voltage and includes an under-voltage detector having an output terminal. The under-voltage detector outputs a UVLO signal when the supply voltage is below a low-to-high threshold value, and does not output the UVLO signal when the supply voltage is above the low-to-high threshold value. The totally-GaN-based driver includes a pulse stretcher having an input terminal coupled to the output terminal of the under-voltage detector, and an output terminal for outputting a stretched_UVLO signal for a predetermined amount of time after the supply voltage first rises above the low-to-high threshold value.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Pramit SARKAR, Manish SHAH