Abstract: A cell-based integrated circuit comprises a first supply voltage terminal and a second supply voltage terminal. A standard cell comprising a thyristor circuit comprising a first input inputs the first supply voltage. A second input inputs the second supply voltage. A first output outputs a first output voltage corresponding to the first supply voltage and a second output to output a second output voltage corresponding to the second supply voltage.

Abstract: A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of an opposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor.

Abstract: A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of anopposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor.

Abstract: A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of an opposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor.

Abstract: Implementations are presented herein that include a level shifter circuit.

Abstract: Implementations are presented herein that include a level shifter circuit.

Abstract: A cell-based integrated circuit comprises a first supply voltage terminal and a second supply voltage terminal. A standard cell comprising a thyristor circuit comprising a first input inputs the first supply voltage. A second input inputs the second supply voltage. A first output outputs a first output voltage corresponding to the first supply voltage and a second output to output a second output voltage corresponding to the second supply voltage.

Abstract: A method of switching on a voltage supply of a voltage domain of a semiconductor circuit includes switching, initially, a first switchable element, via which elements of the voltage domain are connected to a supply voltage of the semiconductor circuit, to a conductive state. The method includes switching, after a predetermined period of time, a second switchable element, via which elements of the voltage domain are connected to the supply voltage of the semiconductor circuit, to a conductive state. The driving capacity of the first switchable element is less than the driving capacity of the second switchable element.

Abstract: A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of an opposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor.

Abstract: A True Single Phase Clock flip-flop is configured to operate in an evaluating and a hold mode. The flip-flop comprises an input stage having an input node and a first output node. The flip-flop further comprises a middle stage having a second output node and an output stage having a third output node. The flip-flop further comprises a reset functional block which is switchable between an activated and a deactivated mode. Said reset functional block resets said flip-flop when activated and is configured to synchronous exit out of reset when switched from its activated to its deactivated mode so that an output signal of said flip-flop is only up-dated when said flip-flop changes to its next evaluating mode.

Abstract: A method of switching on a voltage supply of a voltage domain of a semiconductor circuit includes switching, initially, a first switchable element, via which elements of the voltage domain are connected to a supply voltage of the semiconductor circuit, to a conductive state. The method includes switching, after a predetermined period of time, a second switchable element, via which elements of the voltage domain are connected to the supply voltage of the semiconductor circuit, to a conductive state. The driving capacity of the first switchable element is less than the driving capacity of the second switchable element.

Abstract: The invention relates to a semi-conductor component with a comparator circuit assembly (1), as well as a comparator circuit assembly (1), in particular a comparator/receiver circuit assembly, comprising a first and second transistor (8, 9), whose control inputs are connected with each other, and a third transistor (10), to whose control input an input signal (VIN) is applied, and which is connected to the first transistor (8), and a fourth transistor (11), to whose control input a reference signal (VREFmod, VER) is applied, and which is connected to the second transistor (9), whereby the control input of the third transistor (10) is connected to the control inputs of the first and second transistor (8, 9) via a coupling device (22).

Abstract: The invention is aimed at providing a novel semi-conductor component, as well as a novel process for reading test data. There is a process for reading test data is made available, including reading test data generated during a semi-conductor component test procedure from at least one test data register of a semi-conductor component, storing the test data in at least one useful data memory cell provided on the semi-conductor component, and reading the test data from the at least one useful data memory cell.

Abstract: The invention refers to a comparator, and to a method for amplifying an input signal. The input signal is amplified by providing, by use of a first current source/sink, a first current to an output node, sinking, by use of a third current source/sink, a third current from the output node, and inputting the input signal to a control input of the third current source/sink, whereby a control input of the first current source/sink is connected to the third current source/sink by a clamping capacitor, such that an output node load capacitance, representing a second current source/sink, is rapidly charged when the input signal changes its state in a first direction, and is rapidly discharged when the input signal changes its state in a second direction.

Abstract: An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

Abstract: Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

Abstract: Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)

Abstract: The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the data clock signal, and a serial-parallel converter is used to put together a prescribed number of data items from the data read in to give a prescribed number of words from data words having the prescribed word length. To make transferring the data from one synchronization area to another synchronization area, and resynchronization thereof, more reliable, the invention involves an interface memory copying the at least one data word from the serial-parallel converter upon receipt of a copy signal which is synchronous with the data block signal and outputting it to a bus upon receipt of an output signal which is synchronous with the system clock signal.

Abstract: Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which [lacuna] a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)

Abstract: Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.